Milpitas, CA. February 4, 2021 – Alchip Technologies, Limited, the high-performance computing ASIC leader, revealed today that demand for post-GDSII backend services has increased exponentially across all high-performance computing ASIC applications. The company is meeting this uptick with invested emphasis on production, packaging and test and assembly services.
“Given the complex demands place on today’s high-performance computing ASICs, it’s not surprising that there’s a keen focus on proven production, packaging, and test and assembly capabilities. These once-pedestrian practices are now highly prized for their capabilities to wring out every last nth of performance power and area,” observes Johnny Shen, Alchip Technologies’ President & CEO.
Backend Keys Last Mile Success
As a result, Alchip’s post-GDSII services are experiencing high demand as systems and OEM companies face both technology challenges and engineering talent limitations associated with traditional backend services. Sophisticated high-performance frontend design resources are expensive and, depending on geographic location, somewhat scarce. The result is an uptick in companies outsourcing production, packaging, test and assembly responsibilities to ASIC companies who are far more experienced in these strategic areas.
“Packaging isn’t packaging anymore,” declares Leo Cheng, Senior Vice President of Engineering at Alchip. “With today’s design complexity, packaging has become the most cost/efficient route to increasing performance, lowering power consumption and meeting real estate constraints. Every project, no matter how small, requires backend capabilities to conquer today’s advanced manufacturing technology complexity.”
“Our key to success is knowing how to target advanced technology so that we can collaborate with the customers to develop a manufacturing protocol that is done ‘their way’ rather than one monolithic approach that is done our way,” explains Mr. Shen.
Alchip has elevated its packaging capabilities to include Chip-on-Wafer-on-Substrate (CoWoS®) first developed by TSMC and this Spring is expected to announce a true 2.5D INFO capability.
Alchip’s CoWoS process runs on dedicated tooling and demonstrates IP performance equivalent to that of an original design. The process also includes online debugging and active thermal control. The company’s in-house design substrate design capabilities assure compliance with all system requirements and establishes the frame work for critical foundry-to-final test flow.
The company has also unveiled a two sign-off verification options to accommodate both design economics and enhanced yield objectives. Standard sign-off verification includes DRC/LVS/ERC checks that guard against fatal manufacturing error. A second design options calls for additional focus on Electrical, DFT, STA and/or clock verification, depending on specific customer requirements.
“Backend design is really a global challenge and that’s why we have located a dedicated team in Hsin-Chu, Taiwan. That’s where all of the foundry, packaging and test innovation is taking place so we literally have feet on the street within an of all the innovators. We’ve streamlined our process because of this proximity and are passing along those cost advantages to our high-performance computing ASIC partners,” Cheng explained.
Alchip’s has aligned the backend of its high-performance computing ASIC services to tackle the increased for production, packaging, test and assembly that has emerged with transition to 5nm and below advanced technology nodes.
“Given the complex demands place on today’s high-performance computing ASICs, it’s not surprising that there’s a keen focus on proven production, packaging, and test and assembly capabilities. These once-pedestrian practices are now highly prized for their capabilities to wring out every last nth of performance power and area,” observes Johnny Shen, Alchip Technologies’ President & CEO.
Backend Keys Last Mile Success
As a result, Alchip’s post-GDSII services are experiencing high demand as systems and OEM companies face both technology challenges and engineering talent limitations associated with traditional backend services. Sophisticated high-performance frontend design resources are expensive and, depending on geographic location, somewhat scarce. The result is an uptick in companies outsourcing production, packaging, test and assembly responsibilities to ASIC companies who are far more experienced in these strategic areas.
“Packaging isn’t packaging anymore,” declares Leo Cheng, Senior Vice President of Engineering at Alchip. “With today’s design complexity, packaging has become the most cost/efficient route to increasing performance, lowering power consumption and meeting real estate constraints. Every project, no matter how small, requires backend capabilities to conquer today’s advanced manufacturing technology complexity.”
“Our key to success is knowing how to target advanced technology so that we can collaborate with the customers to develop a manufacturing protocol that is done ‘their way’ rather than one monolithic approach that is done our way,” explains Mr. Shen.
Alchip has elevated its packaging capabilities to include Chip-on-Wafer-on-Substrate (CoWoS®) first developed by TSMC and this Spring is expected to announce a true 2.5D INFO capability.
Alchip’s CoWoS process runs on dedicated tooling and demonstrates IP performance equivalent to that of an original design. The process also includes online debugging and active thermal control. The company’s in-house design substrate design capabilities assure compliance with all system requirements and establishes the frame work for critical foundry-to-final test flow.
The company has also unveiled a two sign-off verification options to accommodate both design economics and enhanced yield objectives. Standard sign-off verification includes DRC/LVS/ERC checks that guard against fatal manufacturing error. A second design options calls for additional focus on Electrical, DFT, STA and/or clock verification, depending on specific customer requirements.
“Backend design is really a global challenge and that’s why we have located a dedicated team in Hsin-Chu, Taiwan. That’s where all of the foundry, packaging and test innovation is taking place so we literally have feet on the street within an of all the innovators. We’ve streamlined our process because of this proximity and are passing along those cost advantages to our high-performance computing ASIC partners,” Cheng explained.
Alchip’s has aligned the backend of its high-performance computing ASIC services to tackle the increased for production, packaging, test and assembly that has emerged with transition to 5nm and below advanced technology nodes.