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High-NA might be last-gen litho

pgerven

New member
Apologies for the shameless self-promotion, but I believe folks around here will appreciate my interview with ASML CTO Martin van den Brink. He confirmed that ASML is looking into >0.7 NA EUV litho as a potential successor to high-NA, as hinted at by Intel's Mark Phillips. However, Van den Brink is not at all convinced hyper-NA will ever make it into production. In other words, high-NA might mark the end of the semiconductor lithography roadmap.

Check out the interview on Bits&Chips
 
Apologies for the shameless self-promotion, but I believe folks around here will appreciate my interview with ASML CTO Martin van den Brink. He confirmed that ASML is looking into >0.7 NA EUV litho as a potential successor to high-NA, as hinted at by Intel's Mark Phillips. However, Van den Brink is not at all convinced hyper-NA will ever make it into production. In other words, high-NA might mark the end of the semiconductor lithography roadmap.

Check out the interview on Bits&Chips
The polarization impact from such high NA is too restrictive.

The 16-18 nm pitch target by High-NA is already questionable.

 
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Curious - when it is stated that Hyper-NA might never be economically feasible - I assume that’s ‘full picture’ economics - throughput, energy requirements, etc? And not referring to the initial machine cost only?

Thanks
 
"But how much room is left in the market for even larger lenses? Could we even sell those systems? I was paranoid about high-NA and I’m even more paranoid about hyper-NA. If the cost of hyper-NA grows as fast as we’ve seen with high-NA, it will pretty much be economically unfeasible. Although, in itself, that’s also a technological issue. And that’s what we’re looking into.”
 
Some of Intel's statements on the High-NA tool status indicate it's not even fully into development yet:


IC: When I was in Intel’s D1X Fab (the development fab), I did get to see the EUV machines up close. I touched one and then got told off for it! It was also fun to look inside it as well, because you guys are still installing so many of these machines. When High-NA comes around, if by some reason it's not ready, or there are other challenges, could I surmise from what you're saying that for the future nodes that are along those timeframes, if they are ready earlier, the idea is to bring it in earlier? Or if it doesn't arrive as intended, that there's flexibility for those layers that may or may not have been High-NA?

AK: Correct. We're aiming to introduce it in more in 2025, and we're setting up our processes so that if for some reason High-NA is not ready, then we will be able to continue without it. As soon as High-NA is ready, then we'll be able to put it into our product and use it.

IC: Intel already has orders in for High-NA machines from ASML. The first-gen NXE:5000 for development, and it's just been announced that you've ordered a second generation NXE:5200. What exactly will you be using the High-NA development machine for?

AK:
The NXE:5000 is currently being built for us at ASML. When I visited ASML late last year, I saw the pieces as it was being built and put together. But we're also working with ASML, and as soon as their first High-NA tool is available for us, we will be running some of our experiments in their lab on that. so that will we will be starting as early possible. So as soon as the NXE:5000 docks, they will be able to cut over and then run it in our own Fab. So we have a very active team working right now with ASML, and those teams are working through all the line items that need to get done, so that by the time the NXE:5000 arrives, that we're good to go and good to go on the development work in our Fab.

IC: When I'm quoted how long it takes to install an EUV machine and tune it, usually it's about six months for each, will the first-gen High-NA UV machine be similar or are you trying to improve that?

AK:
We're always striving to drive down the qual (qualification) time. Right now, I'm not in a position to quote what its final qual time will be, but we will be taking as much as possible in learning out of the install quals of the 0.33 NA (regular EUV), basically to apply them to the 0.5 NA (High-NA). There is work to be done, is the simplest way of putting it.
 
So X-Ray lithography is off the table? It has looked like that since IBM played with XR in the 1990s, and photons outran them, so to speak.
 
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So X-Ray lithography is off the table? It's has looked like that since IBM played with XR in the 1990s, and photons outran them, so to speak.
For a while there was talk of BEUV (6.7 nm) but it seems that was not considered ahead of increasing NA (at same 13.X wavelength). Presumably, shorter wavelength would have more leftover energy (i.e., secondary electron) complications.
 
Apologies for the shameless self-promotion, but I believe folks around here will appreciate my interview with ASML CTO Martin van den Brink. He confirmed that ASML is looking into >0.7 NA EUV litho as a potential successor to high-NA, as hinted at by Intel's Mark Phillips. However, Van den Brink is not at all convinced hyper-NA will ever make it into production. In other words, high-NA might mark the end of the semiconductor lithography roadmap.

Check out the interview on Bits&Chips
Next to higher NA I thought ASML was also still looking at lower wavelength. Is thiat now officially from the table ?
 
Hard times indeed. It took more than 10 years to adopt EUV from ArF-i. Tons of new technologies, from materials to methodologies were required to introduce EUVs to Fabs. Even with these efforts, EUVs still suffer from throughput and power consumption.

I'm not even sure if High NA EUVs really 'productive'. Even if we find applications which benefit from it, then there will be new challenges from materials (post Cu, etc). These also require breakthroughs in etching and deposition...etc.

This is a part of the reason why Foundries are relying on a GAA(Nanasheet) these days. Stacking up instead of making smaller features. But this also introduces new challenges like power density and thermals. Can't really imagine what will happen after 10 years.
 
Next to higher NA I thought ASML was also still looking at lower wavelength. Is that now officially off the table?

13.5 benefits from a number of coincidences. There are a number of deep-shell transitions which all cluster around 13.5 making a stronger emission narrow enough to use the same mirror. This is not found in any shorter wavelength thermal plasma system, so they would probably need to go to beam-line source, unproven.

Another coincidence is how the Si-Mo mirror layers work. There is a peculiar shift in absorption properties which has an edge in that range which happens to make the interference stronger. Otherwise most materials have an optical index very close to 1.0 in the EUV. This means that if you move to another wavelength you might not find any pairing that makes mirrors as good, so they would need to figure out the optics with many fewer surfaces.

It is not impossible, perhaps some conceptual breakthroughs will solve it, but at the moment there is no obvious feasibility at shorter wavelengths.
 
Hard times indeed. It took more than 10 years to adopt EUV from ArF-i. Tons of new technologies, from materials to methodologies were required to introduce EUVs to Fabs. Even with these efforts, EUVs still suffer from throughput and power consumption.

I'm not even sure if High NA EUVs really 'productive'. Even if we find applications which benefit from it, then there will be new challenges from materials (post Cu, etc). These also require breakthroughs in etching and deposition...etc.

This is a part of the reason why Foundries are relying on a GAA(Nanasheet) these days. Stacking up instead of making smaller features. But this also introduces new challenges like power density and thermals. Can't really imagine what will happen after 10 years.
For sure the early research for EUV was going on in the 80s with the main effort starting in the early 00s.

As for High NA the path forward is much easier than it was with EUV (since large parts of the tool are unchanged). The benefits should also be pretty big. Throughput will objectively be better as will minimum resolution. This would allow for a high NA tool to be more than twice as expensive as a EUV tool, while still making financial sense. Yields should also be better because you won't have to align multiple mask layers in the same way you would for EUV double patterning.

GAA is mostly a leakage thing (just like finfets). The stacking is a secondary benefit (it isn't really making the std cell sizes that much smaller either). Also keep in mind that the stacked wires/sheets/ribbons are not separate transistors they are all connected in parallel (just like the fins on a finfet).
 
For sure the early research for EUV was going on in the 80s with the main effort starting in the early 00s.

As for High NA the path forward is much easier than it was with EUV (since large parts of the tool are unchanged). The benefits should also be pretty big. Throughput will objectively be better as will minimum resolution. This would allow for a high NA tool to be more than twice as expensive as a EUV tool, while still making financial sense. Yields should also be better because you won't have to align multiple mask layers in the same way you would for EUV double patterning.

GAA is mostly a leakage thing (just like finfets). The stacking is a secondary benefit (it isn't really making the std cell sizes that much smaller either). Also keep in mind that the stacked wires/sheets/ribbons are not separate transistors they are all connected in parallel (just like the fins on a finfet).
GAA helps by opening up new scaling paths. N-P distance reduction(no more dummies), gate length reduction(thanks to better leakage control), and CFET(N-P stacking).
We can also consider GAA as a 'vertically stacked multi-fin device', making multi-fin device use 1-fin space by stacking up. It's also a kind of scaling booster.

As for a High NA, I also agree but can't stop thinking that gains from new lithography are not applied universally(to all chips) like before. Miss good old days
 
As for High NA the path forward is much easier than it was with EUV (since large parts of the tool are unchanged). The benefits should also be pretty big. Throughput will objectively be better as will minimum resolution. This would allow for a high NA tool to be more than twice as expensive as a EUV tool, while still making financial sense. Yields should also be better because you won't have to align multiple mask layers in the same way you would for EUV double patterning.
Not true, mostly. Some other points mentioned here: https://semiwiki.com/lithography/303156-cautions-in-using-high-na-euv/

Optics is changed to anamorphic and the last mirror has a hole in it, unavoidably.
The field size is smaller, so the benefits are very product-dependent.
Resist is thinner, so stochastic effects would be worse.
Polarization becomes important where the high NA is expected to be necessary, e.g., 16-18 nm pitch, as mentioned above. Some more details here: https://www.linkedin.com/pulse/growing-significance-polarization-euv-lithography-frederick-chen
 
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GAA helps by opening up new scaling paths. N-P distance reduction(no more dummies), gate length reduction(thanks to better leakage control), and CFET(N-P stacking).
We can also consider GAA as a 'vertically stacked multi-fin device', making multi-fin device use 1-fin space by stacking up. It's also a kind of scaling booster.

As for a High NA, I also agree but can't stop thinking that gains from new lithography are not applied universally(to all chips) like before. Miss good old days
1. My point was more so that GAA is a requirement for shrinks if you don't want leakage to be ridiculous. You can still make smaller finfets, but as TSMC is learning at N3 that is hard (not that GAA is easy either). If estimates are to be believed N2 and 20A supposed to have similar density despite the architecture change, thus they are mostly offering extra P&P.

2. In the future you are probably right as you have a similar footprint as 1 fin finfets, and greater flexibility in design by messing with sheet sizes.

3. CFET is not inherently GAA and it can be done with any kind of transistor architecture (see devices that have gaa transistors stacked upon finfet devices)

4. It's not exactly like EUV is applicable to most chips or is even used for most of the layers on the most advanced products.
 
Not true, mostly. Some other points mentioned here: https://semiwiki.com/lithography/303156-cautions-in-using-high-na-euv/

Optics is changed to anamorphic and the last mirror has a hole in it, unavoidably.
The field size is smaller, so the benefits are very product-dependent.
Resist is thinner, so stochastic effects would be worse.
Polarization becomes important where the high NA is expected to be necessary, e.g., 16-18 nm pitch, as mentioned above. Some more details here: https://www.linkedin.com/pulse/growing-significance-polarization-euv-lithography-frederick-chen
Thanks for the extra nuance! Optics is not my field of specialty, so forgive my ignorance; but if I understand your article High NA will be most useful for smaller dies where the higher edge defect density is less of an issue/you can fit more dies per reticle.
 
High NA will be most useful for smaller dies where the higher edge defect density is less of an issue/you can fit more dies per reticle.
The High-NA field is 26 mm x 16.5 mm vs. the 0.33NA field of 26 mm x 33 mm. If the die size is larger than 26 mm x 16.5 mm (429 mm2), it has to use two exposures, whete the boundary likely cuts through circuit wires.
 
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