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GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

VCT

Member

Earlier than TSMC?

Based on past information. Samsung's 3nm GAA transistor density is about the same as TSMC 5nm.
Is that information still update and correct?

TSMC-Samsung-Intel-Nodes.jpg
 
Last edited:

Daniel Nenni

Admin
Staff member

Earlier than TSMC?

Based on Semiwiki's information. Samsung's 3nm GAA transistor density is about the same as TSMC 5nm.
Is that information still update?

Yes, Samsung did their foundry press briefing on Tuesday. It was interesting.

"GAA is ready for customers' adoption - 3nm MP in 2022, 2nm in 2025 With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, MultiBridge-Channel FET (MBCFETTM), is essential for continuing process migration. Samsung's first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance, and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production. Samsung is scheduled to start producing its customers' first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025."

Hopefully Samsung 2GAP will be competitive to TSMC N3 because Samsung 3GAP is not.

Samsung Foundry 2021.jpg
 
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VCT

Member
Yes, Samsung did their foundry press briefing on Tuesday. It was interesting.

"GAA is ready for customers' adoption - 3nm MP in 2022, 2nm in 2025 With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, MultiBridge-Channel FET (MBCFETTM), is essential for continuing process migration. Samsung's first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance, and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production. Samsung is scheduled to start producing its customers' first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025."

Hopefully Samsung 2GAP will be competitive to TSMC N3 because Samsung 3GAP is not.

View attachment 540
Hi Dan,
Is your roadmap above from yesterday presentation?
"Hopefully Samsung 2GAP will be competitive to TSMC N3 because Samsung 3GAP is not."

Your voice on Podcast are so young. : ) I was shocked.
 

jorgequinonez

New member
I was reading based on density density that Samsung's 4nm (not sure if it was lpe or lpp) was barely equivalent to TSMC 6nm node. I think it was on https://fuse.wikichip.org.

Using nanometer in the node name after a number is just marketing nowadays. The only thing you can ascertain is that a smaller number is more dense.
 

blueone

New member
I wonder... how important is it for future competitiveness to achieve a GAA process earlier at production scale, rather than squeezing the last drop of density from a FinFET process? Are we looking at a potential Samsung leapfrog around TSMC? (Assuming Samsung can execute.)
 

Daniel Nenni

Admin
Staff member
I wonder... how important is it for future competitiveness to achieve a GAA process earlier at production scale, rather than squeezing the last drop of density from a FinFET process? Are we looking at a potential Samsung leapfrog around TSMC? (Assuming Samsung can execute.)

Given the density difference between Samsung 3 and TSMC 3 I think you have the answer to that question.

You should also know that design tools and IP have not caught up with GAA yet which is why Apple, AMD, Nvidia, Qcom, etc... are staying with TSMC for 3nm.

So, yes, congratulations to Samsung for being first to GAA in the lab. It will be interesting to see who gets GAA into HVM first: Samsung, Intel, or TSMC?
 

Paul2

Active member
Given the density difference between Samsung 3 and TSMC 3 I think you have the answer to that question.

You should also know that design tools and IP have not caught up with GAA yet which is why Apple, AMD, Nvidia, Qcom, etc... are staying with TSMC for 3nm.

So, yes, congratulations to Samsung for being first to GAA in the lab. It will be interesting to see who gets GAA into HVM first: Samsung, Intel, or TSMC?
Metal, metal, metal

Devices themselves scaled very well to the point where even an extra line, or two can now be added when needed

Interconnect been lagging dramatically behind transistor scaling.

Intel was supposed to have the densest middle-end, but ran into huge problem with cobalt.

So, it leaves TSMC on the forefront, with Samsung having both lower M0 resolution, as well as more constrained design rules.

I will be very surprised if they actually stayed on pure, conventional copper interconnect, and not tried different liners, and silicides.
 
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