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Faster FPGA verification

Daniel Nenni

Staff member
Henderson, Nevada, USA – June 22nd, 2020 Launched in 2015, and used by about 20% of all VHDL FPGA designers, UVVM is one of the fastest growing verification methodologies in the EDA industry.

Today, design verification accounts for more than half of overall project time. Verification methodologies exist to alleviate this bottleneck, where a methodology will typically include a sequencer (a means of sending data to and controlling a device under test [DUT]), models (expressing how components should behave) and a scoreboard (a means of comparing the DUT’s behaviour against the model’s).

Some solutions have been around for decades. For example, the Universal Verification Methodology (UVM) has its roots in a language developed for verification purposes in 2001. However, UVM is based on the SystemVerilog language whereas about half of the FPGA design community codes in VHDL. For them, a VHDL based verification methodology is faster and more efficient.

It is even better news when it is free / open-source.

For instance, the open-source VHDL verification methodology (OS-VVM) which was launched in 2012, was named the number 1 verification library in 2018 and remains extremely popular. Also, its chief developer, Jim Lewis of Synthworks, works closely with the IEEE VHDL standards group.

A more recent addition to the industry is the Universal VHDL Verification Methodology (UVVM). It was launched in 2015 and has a growing following.

So, what’s the score?

UVVM is a free methodology and library (downloadable from for making structured VHDL-based testbenches. It comprises the following elements: a utility library, a VHDL verification component (VVC) framework and bus functional models (BFMs).

To demonstrate these, it is best to consider a verification scenario. Figure 1 shows the test bench for a simple interrupt controller (IRQC).

This test bench includes the DUT (i.e. the IRQC), which has a clock (clk), a reset (arst), a simple bus interface (SBI), a number (n) of interrupt sources (irq_source(n)) and the resulting interrupt to the CPU (irq2cpu). The test bench also has a clock generator and a test sequencer.


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