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EUV was never going to be single patterning

Fred Chen

Moderator
An investor presentation by ASML near the end of 2014 showed that 7nm was never going to be a single-patterning node even with EUV, but the start of a multipatterning spiral similar to what immersion is going through now. Hence, the need to develop high-NA with Zeiss. Even then, there would be no recovery to single patterning, as shown in the overlay tree below.

From slide 49:
https://staticwww.asml.com/doclib/investor/asml_3_Investor_Day-Many_ways_to_shrink_MvdBrink1.pdf

View attachment 19075

So, from this consideration, the throughput and corresponding source power target needs to be doubled, even without considering shot noise yet.
 
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Is this REALLY the case? Suppose that EUV were reliable "enough" and cheap "enough" say in 2019 or so. Obviously the leading edge customers are at that point champing at the bit to get to EUV, whatever it costs.

BUT there's also a whole lot of much lower volume customers stuck at 28nm or so because their volumes don't justify double patterning or worse. If TSMC, GloFo, or Samsung were to offer them 14nm with single-patterning, wouldn't that be an appealing proposition?
Is there some reason why EUV will ALWAYS be so expensive (even after the aggressive pent-up demand of the first year or three is satisfied) that it wouldn't make sense in the sort of scenario I suggest, as just the natural successor to ArF for many (even less demanding) litho tasks?
 
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BUT there's also a whole lot of much lower volume customers stuck at 28nm or so because their volumes don't justify double patterning or worse. If TSMC, GloFo, or Samsung were to offer them 14nm with single-patterning, wouldn't that be an appealing proposition?
Is there some reason why EUV will ALWAYS be so expensive (even after the aggressive pent-up demand of the first year or three is satisfied) that it wouldn't make sense in the sort of scenario I suggest, as just the natural successor to ArF for many (even less demanding) litho tasks?
EUV has many issues on its own already, to justify its use it needs to be able to demonstrate single patterning beyond that of immersion double patterning. Especially with more advanced SADP, double patterning is not something prohibitive but it has been matured, with the help of the memory industry. DRAM uses many double patterning layers, for example. As of today, immersion with double patterning is still the only way for HVM at 40-50 nm pitch. EUV is not fast or clean enough at this point. On the other hand, double patterning also forces foundries to push to the smallest pitches possible in order to reduce cost per transistor. 2 masks to achieve one-third the pitch (yes, it's possible*) is hard to beat. EUV therefore needs to show single patterning scalability below 20 nm half-pitch, which is the 7nm territory. This is where the EUV double patterning question comes in.

*http://www.cerc.utexas.edu/utda/publications/C111.pdf see Fig. 12 wide U-bend. A similar concept is described in US Patent 7846849.
 
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Layer sub-patterns with exclusive SMO

Mixtures of different sub-pattern layouts at different locations with different optimized (pupil) sources can occur in the same layer, as expected for random logic BEOL layers with same minimum pitch. That could mean EUV needs multi-patterning due to the need for separate optimized pupils. Some recent published examples are listed below.

The effect of multiple included layer sub-patterns in SMO was demonstrated in a paper from SPIE 2017 (W. Gillijns et al., reference below). Here the anchor pitch is 32 nm while the overlay mark is a 200 nm pitch 100 nm feature; it already took some optimization to get them together with the 2-bar in the same focus window without shifting more than 0.8 nm. However, including more sub-pattern clips from the same layer into the optimization resulted in some sub-patterns shifting up to 1 nm in the same focus window.

More recently, ASML/IMEC/TEL showed in an SPIE Photomask 2018 paper (D. Rio et al., reference below) that SMO was more effective in addressing tip-to-tip printability with a lower illumination efficiency of the pupil (i.e., more light is discarded, due to lower pupil fill). Despite this tip-to-tip improvement, the SMO with a weighted optimization for line-space gratings and tip-to-tip gratings only did not improve printability for non-grating parts of a 32 nm pitch logic clip, e.g., where one side of the dense trench is a gap.
File:Different_EUV_SMOs.png


References:

J. Mulkens, J. Karssenberg, H. Wei, M. Beckers, L. Verstappen, S. Hsu, and G. Chen, "Across Scanner Platform Optimization to enable EUV Lithography at the 10-nm Logic Node," Proc. SPIE vol. 9048, 90481L (c) 2014 SPIE.

X. Liu, R. Howell, S. Hsu, K. Yang, K. Gronlund, F. Driessen, H-Y. Liu, S. Hansen, K. van Ingen Schenau, T. Hollink, P. van Adrichem, K. Troost, J. Zimmermann, O. Schumann, C. Hennerkes, and P. Graupner, "EUV source-mask optimization for 7 nm node and beyond," Proc. SPIE vol. 9048, 90480Q (c) 2014 SPIE.

C. Tabery, J. Ye, Y. Zou, V. Arnoux, P. Raghavan, R-H. Kim, M. Cote, L. Mattii, Y-C. Lai, and P. Hurat, "In-design and signoff lithography physical analysis for 7/5nm," Proc. SPIE vol. 10147, 1014705 (c) 2017 SPIE.

W. Gillijns, L. E. Tan, Y. Drissi, V. Blanco, D. Trivkovic, R. H. Kim, E. Gallagher, and G. McIntyre, "Reticle enhancement techniques towards iN7 Metal2," Proc. SPIE vol. 10143, 1014314 (c) 2017 SPIE.

D. Rio, V. Blanco, J.-H. Franke, W. Gillijns, M. Dusa, E. De Poortere, P. Van Adrichem, K. Lyakhova, C. Spence, E. Hendrickx, S. Biesmans, K. Nafus, "EUV pupil optimizations for 32nm pitch logic structures," Proc. SPIE vol. 10809, 108090N (c) 2018 SPIE.
 
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Through-slit SMO (LithoVision 2017)

An interesting update at LithoVision 2017 by Mentor Graphics (Director Dr. John Sturtevant), among other interesting things, referred to variation of aberrations (indicated by Zernike coefficients) across tools and across slit positions. Such aberrations require SMO (source-mask optimization) corrections, per tool, per slit position (essentially multiple patterning by one mask per corrected slit position).

Mentor Graphics Director Details Challenges for Edge Placement Control in 2020

This in fact could have been anticipated years ago: <title>Modeling and experiments of non-telecentric thick mask effects for EUV lithography</title> | Chiew-Seng Koay and Greg McIntyre - Academia.edu and cross-slit aberration variations in EUV tools are generally acknowledged now.

NXE 3400 aberrations are still comparable to older NXE 3350 models: http://pfwww.kek.jp/PEARL/EUV-FEL_Workshop2/Proceedings/01_Lercel.pdf (slide 9) The thermal aspects have not even been considered yet.

At different slit positions, there would be different 3D shadowings of the same feature thick mask patterns. Thus, the SMO would need to be correspondingly different at different slit positions. (Update: This has been confirmed in Z. Zhang et al., Optics Express, vol. 29, 5448 (2021).)

The different slit position exposures also would need to be stitched together.

Background details: An aberration is a deviation of the wavefront from the target, in other words, the illumination direction is off. This will impact the depth of focus (for k1<0.5), unless the pitch is retargeted. OPC involving feature resizing or repositioning does not affect this. But it is not tolerable for design for the minimum metal pitch to vary from 36 to 42 nm at different slit positions, differently for each EUV tool. So the illumination must be varied for different slit positions, different for each EUV tool. On each tool, the stitching of multiple mask exposures should be expected.
 
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An SPIE 2018 paper from Mentor Graphics indicated that with SMO application to the 24-36 nm pitch metal layers, it was preferred to use EUV as a second exposure for cutting rather than as a single standalone exposure. A part of this is the pattern diffraction itself independent of EUV, but 3D mask effects are EUV-specific.

Reference:

R. K. Ali, A. H. Fatehy, N. Lafferty, and J. Word, "Ultimate patterning limits for EUV at 5nm node and beyond," Proc. SPIE vol. 10583, 1058321 (c) 2018 SPIE.

https://www.spiedigitallibrary.org/...ANJy4Gmd3Q6KcdrT6_sguiKJABb5ptDf3Vqblm_Yq9-8K
 
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We had some recent confirmations that multipatterning is inevitable even for EUV if it is implemented in the near term. The first was from ASML at the June 2018 EUVL Workshop presentation by Anthony Yen:

View attachment 22942

The second is from the upcoming SPIE Advanced Lithography conference this month:

Printability study of EUV double patterning for CMOS metal layers
Paper 10957-21
Time: 4:10 PM - 4:30 PM
Author(s): Danilo De Simone, IMEC (Belgium); Arjun Singh, GLOBALFOUNDRIES Europe Ltd. (Belgium); Geert Vandenberghe, IMEC (Belgium)

The impending introduction of EUV lithography into high volume manufacturing at the 7 nm CMOS technology node promises the fulfilment of more than three decades of research and development. However, printing defect-free photoresist features with k1 < 0.4 or line-space pitch < 34 nm using 0.33 NA exposure tools is proving more challenging than originally anticipated. With the introduction timeline of 0.55 NA exposure tools currently unclear, it compels us as an industry to develop EUV multiple patterning strategies for < 34 nm pitch metal layers which are needed to continue area scaling in future 5 nm and/or 3 nm technology nodes. Pursuing EUV-SADP strategies necessitates electrically undesirable dummification of metal wires and the employment of 2 additional masks for self-aligned cutting/blocking of wiring features which may prove cost prohibitive. Therefore, in this study we explore the printability in photoresist of two color EUV LELE or (litho-etch)2 patterns which may be further developed into self-aligned LELE patterning methods. Using both with simulations and experiments, we examine the impact of image and resist tonality on the printability of minimum line and space for metal wire features. We evaluate the printability of these features based on LCDU, LER, LWR and stochastics defects. Additionally, as EUV exposure time per mask is expected to be a major cost contributor, we quantitatively determine the impact of resist photo-speed on the printability of these two color LELE features.
 
A discussion with Moshe Dokejsi reminded me back to this topic. Given that the illumination slit shape on the reticle is an arc, the actual illumination angle is rotated azimuthally through the arc. So in the slit center, your illumination may be optimized for 36 nm pitch, but at the edge, after a 24 degree arc rotation, 40 nm pitch is preferred (cos(24deg) ~ 0.9). So even without aberration considerations, the different illumination in a separate exposure is still required. (Update: This has been confirmed in Z. Zhang et al., Optics Express, vol. 29, 5448 (2021).)

To get a picture of this: https://electroiq.com/2008/10/under...mage-variations-in-full-field-exposure-tools/

An additional effect, mask-induced pupil apodization,* results from different reflectance for different angles at different wavelengths. This produces rotation sensitivity even for rotationally symmetric illumination shapes like annular.

*References:
N. Davydova et al., "Mask aspects of EUVL imaging at 27nm node and below," Photomask Technology 2011, ed. by W. Maurer and F. E. Abboud, Proc. of SPIE vol. 8166, 816624 (c) 2011 SPIE.

N. Davydova et al., "EUVL mask performance and optimization," 28th European Mask and Lithography Conference, ed. by U. F. W. Behringer and W. Maurer, Proc. of SPIE vol. 8352, 835208 (c) 2012 SPIE.
 
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This paper summarizes why the quirks of EUV optics make double exposure (possibly quadruple exposure for 2D) a more natural practice.


Background: In extreme ultraviolet lithography, the printable feature density is limited by stochastic defectivity, which can be reduced by increasing the optical contrast. The photomask induces pole-specific aerial image offsets. Consequently, illumination settings with multiple poles lead to contrast loss and focus offsets between different features.

Aim: We aim to mitigate the contrast loss and best focus offsets between different features.

Approach: Illumination was decomposed into monopoles. Each monopole was exposed separately using a fraction of the total dose. Each exposure was shifted by its pole-specific image offset to mitigate 3D mask effects.

Results: Single monopoles mitigate contrast loss and best focus shifts, but in defocus, they suffer from aerial image shifts and distortions. Multiple aligned monopole exposures conserve these advantages but mitigate the problems in defocus. Because each monopole is exposed with only a fraction of the dose, the throughput penalty is limited to the scanner overhead.

Conclusions: A multiple monopole exposure scheme can increase contrast, align the best foci, and mitigate single monopole exposure constraints. Additionally, it offers an improved pattern placement control through dose control knobs.
 
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This paper summarizes why the quirks of EUV optics make double exposure a more natural practice.


Background: In extreme ultraviolet lithography, the printable feature density is limited by stochastic defectivity, which can be reduced by increasing the optical contrast. The photomask induces pole-specific aerial image offsets. Consequently, illumination settings with multiple poles lead to contrast loss and focus offsets between different features.

Aim: We aim to mitigate the contrast loss and best focus offsets between different features.

Approach: Illumination was decomposed into monopoles. Each monopole was exposed separately using a fraction of the total dose. Each exposure was shifted by its pole-specific image offset to mitigate 3D mask effects.

Results: Single monopoles mitigate contrast loss and best focus shifts, but in defocus, they suffer from aerial image shifts and distortions. Multiple aligned monopole exposures conserve these advantages but mitigate the problems in defocus. Because each monopole is exposed with only a fraction of the dose, the throughput penalty is limited to the scanner overhead.

Conclusions: A multiple monopole exposure scheme can increase contrast, align the best foci, and mitigate single monopole exposure constraints. Additionally, it offers an improved pattern placement control through dose control knobs.

So this leaves DUV 65nm, or 45 immersion as last single expo nodes?
 
How many dry fabs there are left who can do 65?

I want to count how many fabs are left for mortals to use. I recently been in talks with people who decide on 65 vs 40 for an MCU. With 65 they have a portable design, and for 45 they will have to marry TSMC's prop process + more mask costs. TSMC still takes a somewhat noticeable premium for 45 vs. other fabs.
 
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How many dry fabs there are left who can do 65?

I want to count how many fabs are left for mortals to use. I recently been in talks with people who decide on 65 vs 40 for an MCU. With 65 they have a portable design, and for 45 they will have to marry TSMC's prop process + more mask costs. TSMC still takes a somewhat noticeable premium for 45 vs. other fabs.
I'm not sure Intel kept its 65nm until now, but at some other places 55nm is often where 65nm migrates to.
 
I want to count how many fabs are left for mortals to use. I recently been in talks with people who decide on 65 vs 40 for an MCU. With 65 they have a portable design, and for 45 they will have to marry TSMC's prop process + more mask costs. TSMC still takes a somewhat noticeable premium for 45 vs. other fabs.
So "for mortals to use" meaning an ordinary low-end low-cost (by today's standards) process that doesn't require ultra-high volumes to overcome initial investments of masks / EDA tools / learning how to work with the quirks of said process, and has at least two fabs so there is some competitive pricing pressure? Or are there some other nuances you have in mind?
 
So "for mortals to use" meaning an ordinary low-end low-cost (by today's standards) process that doesn't require ultra-high volumes to overcome initial investments of masks / EDA tools / learning how to work with the quirks of said process, and has at least two fabs so there is some competitive pricing pressure? Or are there some other nuances you have in mind?

Yes exactly. I have no precise numbers, but I would say a majority of American semis outside of MNC league can only afford 200mm. Sub 500 wafers per year is un-survivable economically on 300mm for low markup products.

This chips https://www.sprintek.com/en/products/keyboard_ic/SK5210.aspx or this one https://www.vlsi.fi/en/products/vs1063.html is a good example of what American 1 man semi companies still do these days.

Tons of designs don't need an economical reason to even go from 180nm to 130nm in most cases.

Even 65 will be a very expensive proposition on sub 1k wpy runs if you still haven't made an initial investment into tooling/learning/IP/EDAs/fab relationship
 
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This paper summarizes why the quirks of EUV optics make double exposure (possibly quadruple exposure for 2D) a more natural practice.


Background: In extreme ultraviolet lithography, the printable feature density is limited by stochastic defectivity, which can be reduced by increasing the optical contrast. The photomask induces pole-specific aerial image offsets. Consequently, illumination settings with multiple poles lead to contrast loss and focus offsets between different features.

Aim: We aim to mitigate the contrast loss and best focus offsets between different features.

Approach: Illumination was decomposed into monopoles. Each monopole was exposed separately using a fraction of the total dose. Each exposure was shifted by its pole-specific image offset to mitigate 3D mask effects.

Results: Single monopoles mitigate contrast loss and best focus shifts, but in defocus, they suffer from aerial image shifts and distortions. Multiple aligned monopole exposures conserve these advantages but mitigate the problems in defocus. Because each monopole is exposed with only a fraction of the dose, the throughput penalty is limited to the scanner overhead.

Conclusions: A multiple monopole exposure scheme can increase contrast, align the best foci, and mitigate single monopole exposure constraints. Additionally, it offers an improved pattern placement control through dose control knobs.
More on this strategy here: Multiple Monopole Exposures: The Correct Way to Tame Aberrations in EUV Lithography?
 
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TSMC says they avoided double patterning on N3E by reducing density:
TSMC also mentioned that three critical layers which required double-patterning with EUV on N3B have been replaced by single-patterning with EUV on N3E. This reduces complexity, costs, and improves cycle times.
 
N5 already had one double patterned layer and the minimum metal pitch disclosed by TSMC would still require double patterning. This statement was moreso that they relaxed pitches enough for 3 of the double patterned layers to move to high dose single exposures. Given the lack of announced DTCO improvements on the standard cell level and the fact that the 2 fin library is as dense as it is, it is a safe assumption that there are probably a bit more single patterned layers and multiple extra double pattered EUV layers on N3E.
 
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