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eSilicon's Design Center in Pavia, Italy is growing and and seeking experienced SerDes related Engineering talent

Sheila

New member
eSilicon serves the $10B+ ASIC design and manufacturing markets for system OEMs and fabless semiconductor companies covering diverse end markets. eSilicon offers design and manufacturing services, along with a rich portfolio of customizable memory IP, high performances IOs and SerDes making it an ideal partner for creating semiconductor-based solutions no matter what the end market, no matter what the process node and no matter how fast the expected volume ramp.

eSilicon's Design Center in Pavia, Italy is growing and and seeking experienced SerDes related Engineering talent.

The Pavia Design center develops a set of high end networking interface functions (IPs) used to connect the large ASICs for high profile customers and also to be licensed to customers who are doing their own ASIC designs.

The main focus is on: 56Gb/s PAM4 modulated, Long Reach (~40dB @ Nyquist freq.) SerDes interfaces for intra-board, board to board and cable connections, next generation 112Gb/s SerDes using the most scaled Si process available on the planet and 2Tbps/mm ultra-short-reach high-speed die-to-die links for 2.5D interconnection of silicon dice on the same passive interposer or through silicon bridges.

If you are:
* High energy, customer focused Engineer with experience in complex, high speed serial interfaces, high end networking IP (SerDes)
* Well regarded by industry colleagues as a collaborator and technical mentor
* Eligible and available to work in Italy (our Pavia office location)
* Fluent in Italian and excellent English skills
* Graduate of Electrical Engineering or similar degree (Bachelors or Masters level) and possess minimum 3 years industry experience

Please submit your CV to links below or contact me directly for more information

SerDes Lab Support Engineer - Technician
Senior Lab Support Engineer for the Application team in Pavia is responsible for all the aspects of Lab management of Pavia’s SerDes and HBM lab. You’ll be the go to person to ensure timely bench and SW bring up and to ensure proper functionality of all the Hardware needed to support customers/demo and internal usage. Submit CV

SerDes Applications Engineers responsible for hardware and testing and validation of the physical layer of high frequency SerDes systems. As product experts, you will be also responsible to define testing architecture, directly support the development team during debug phase and supporting customers with HFSS/ADS simulation for package, interposer and silicon. Submit CV

Senior System and Algorithm Engineers will belong to will work closely with analog, digital and DSP design teams to ensure that system requirements are suitable for efficient implementation and that implemented solutions are actually meeting the given specifications for all the SerDes IP components. Submit CV

Senior Systems and Embedded Software Engineers work closely with the SerDes PHY Architecture and Lab team members to code and verify startup-sequences, calibrations, link optimization and real time background optimization routines, as well as implementing the requested changes to customize the firmware according to customer requests. Submit CV

Senior System and Algorithm Engineers work closely with analog, digital and DSP design teams to ensure that system requirements are suitable for efficient implementation and that implemented solutions are actually meeting the given specifications for all High Speed Serial Interfaces (PAM2/4 56Gb/s Long Reach interface and beyond). Submit CV

Direct candidates only - eSilicon does not accept 3rd party CVs without prior written approval. Contact me for details.
 
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