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eSilicon is hiring Layout Engineers for SerDes team in Pavia, Italy


New member
eSilicon is hiring experienced Layout Engineers to expand its SerDes team located in Pavia, Italy.

Cerchiamo alcuni Analog Layout Engineer per la nostra sede di Pavia. Esperienza pregressa in layout di blocchi ad alta frequenza e/o tecnologia FinFET verranno tenute in particolare considerazione.

If you are up to the challenge of working on highly flexible architecture solutions, power and area efficient design, optimized custom firmware development and careful silicon validation – then consider eSilicon, an environment where team collaboration and attention to customers’ needs are key differentiators.

Experienced Layout Engineers have first hand responsibility for the physical design (i.e. the actual implementation) of Analog and Mixed Signal circuits for High Speed Serializer/Deserializer (SerDes); you will work on high performance analog and high frequency circuits in the most scaled CMOS technologies, interact with designers and drive layout strategies for very complex products.

Primary responsibilities include:
  • Design (i.e. create) the Blocks, Macro Blocks and IP Layout starting from electrical schematics within process technology specific design rules.
  • Perform top level placement and routing.
  • Identify best performance-effective solution working in team with design engineers.
  • Drive layout methodologies and best practices to assure quality of the IP’s.
  • Execute specific working packages according to the deadline interacting with Design Engineering and Project Management.
  • Coach or coordinate less experienced team members.
  • May direct the work of other team members worldwide.
  • Contribute to project planning and schedules.
  • Guarantee compliance to technology design rules (DRC) and perform
    Physical Verification (LVS) as well as support post-Layout verification and parasitic extraction.
  • Execute Layout Reviews and create proper documentation.
  • Execute Tape Out procedures and task, support or drive Mask Orders submissions.
  • Take ownership of the IP tape out flow
  • Cooperate with the development team on continuous improvement activities (methodologies, checklist, working instructions) and contribute to Technology and Design Methodology improvements.

Profile / Background / Experience Requirements include:

  • Bachelors’ degree in Electrical/Electronic Engineering, Physics or equivalent degree with specific knowledge on microelectronic circuits and technologies
  • 5-8 years or more experience in IC layout design.
  • Knowledge of CMOS/Bipolar technology and related physics.
  • Knowledge of CMOS FinFET technology is a major plus.
  • Good knowledge of electronic circuits and their physical implementation requirements.
  • Deep Knowledge of IC layout best practice for precise analog and mixed signal circuits.
  • Experience with top level floor planning and routing of RF-Analog and Mixed Signal IC is mandatory.
  • Working knowledge of UNIX OS.
  • Excellent knowledge of IC design tools (Virtuoso, Laker, Calibre or similar) is mandatory.
  • Excellent knowledge of parasitic extraction tool including advanced 3D ones.
  • Ability to forecast required effort and resources to meet schedules.
  • Motivated and result oriented, team player with good interpersonal skills.
  • Ability to write reports, technical documentation and routine correspondence in English.
  • Proficient in using Windows, Microsoft Excel, Word, Outlook or equivalent application tools.
  • Fluent Italian, Good spoken and written English required.
  • Must be eligible to work in country (Italy) of hire without restrictions.

Please visit or send me your CV - smarinucci AT eSilicon DOT com

eSilicon is an independent provider of complex FinFET-class ASIC design, custom IP and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete, silicon-proven 2.5D/HBM2 and TCAM platforms for FinFET technology at 14/16nm. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.