After seeing 450+ attendees, several good quality tutorial and papers, lot of exhibitors in the first year, 2nd DVCon India is going to be held on September 10 - 11 at the Leela Palace in Bangalore.
the conference will provide multiple opportunities to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions, and exhibits. Latest information on system design, modelling, and verification. These standards include UVM, SystemC (and variants such as SystemC-AMS, SCV, CCI, and the synthesis subset), SystemVerilog, PSL, AMS assertions and coverage, Verilog, IP-XACT, OCP, UPF etc will be shared.
The conference has two parallel tracks:
Electronic System Level (ESL), including virtual prototypes of electronic systems and SoCs, pre-silicon software development and debug, power and performance analysis with realistic use cases, architectural exploration, high-level synthesis, and interoperability standards for system models
Design and Verification (DV), including design and verification languages, simulation methodologies based on SystemVerilog, including the Universal Verification Methodology (UVM), and complementary technologies such as formal verification, hardware acceleration, in-circuit emulation (ICE), and prototyping
For more information on DVCon India please visit the following link
Special DVCon India Newsletter: July 2015
Regards,
Barun Kumar De
the conference will provide multiple opportunities to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions, and exhibits. Latest information on system design, modelling, and verification. These standards include UVM, SystemC (and variants such as SystemC-AMS, SCV, CCI, and the synthesis subset), SystemVerilog, PSL, AMS assertions and coverage, Verilog, IP-XACT, OCP, UPF etc will be shared.
The conference has two parallel tracks:
Electronic System Level (ESL), including virtual prototypes of electronic systems and SoCs, pre-silicon software development and debug, power and performance analysis with realistic use cases, architectural exploration, high-level synthesis, and interoperability standards for system models
Design and Verification (DV), including design and verification languages, simulation methodologies based on SystemVerilog, including the Universal Verification Methodology (UVM), and complementary technologies such as formal verification, hardware acceleration, in-circuit emulation (ICE), and prototyping
For more information on DVCon India please visit the following link
Special DVCon India Newsletter: July 2015
Regards,
Barun Kumar De
