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Does the Micron layering technology have value in other semis?

Arthur Hanson

Well-known member
With Micron having 232 layers in their memory chips, will the technologies Micron uses have value in semis in general or is strictly for memory? Will this technology be applied in chiplets? Will Micron make memory chiplets for others or will memory remain a largely a seperate component? Any input appreciated, Thanks
 
Micron layering nand is not unique to them. Every nand manufacturer does it and many of them are catching up to micron on the exact layer counts after falling behind a few years ago. This technology has no relevance to “chiplets” because 3D nand is done on a single wafer substrate, and unlike disagrigated designs (chiplets) 3D nand leads to a reduction in cost per fet. “Chiplets” is integrating multiple dies onto the same package via an organic interposer or interposer die. Meanwhile 3D nand is like building a skyscraper of transistors.

Is nand stacking realvent outside of nand flash? Probably, but probably not directly. DRAM is a transistor and a capacitor. Meanwhile nand is one transistor with two gates, so the same scheme cannot be applied for DRAM. This exact technology is also insufficient for logic because unlike nand and DRAM, logic is not just an array. The complex routing needed for logic is incompatible with how nand stacking is done. Furthermore because nand transistors are vertical nanowires, you cannot increase device performance without quickly reducing your transistor density. It is for these reasons that logic is moving to stacks of horizontal nanowires (note not stacked transistors but stacked nanowires on one common gate to get increased effective area at the same footprint) for the initial GAA nodes to get maximum performance per area.

TLDR nand stacking is an awesome technology that the memory guys came up with almost a decade ago when nand could shrink no further to enter a scaling era without any end in sight. Now that DRAM is hitting a wall (although nowhere near as hard as the nand flash wall) they are looking for a similar trick, although the exact solution will likely be very different to accommodate the unique particularities of DRAM. The more variable nature of logic/the need for logic to have good PPW characteristics will make multi layer devices harder to achieve than DRAM. But logic is farther from the scaling wall, and 2 transistor cfet stacks will further stave off the requirement for a more robust multi layer scheme.
 
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Thermal works against you. Spreading out helps routing, heat dissipation. Chiplets and interposers seems like the future to me, not skyscrapers. Just my $0.63
 
Layering technology employed by Mircon is not unique. Massively deployed Monolithic inter-tier vias are something we are investigating for our new low latency, low power data switching platform. Designed around data arrays rather than embedded logic, we are quite excited about the scalability of our data interchange platforms by leveraging similar layering techniques. Vertical data paths also have a thermal benefit that helps us reduce heat. The layering approach is great for scaling interconnections but we are challenged by IO limitations which are only partially offset by advances in copackaged optics.
 
Thermal works against you. Spreading out helps routing, heat dissipation. Chiplets and interposers seems like the future to me, not skyscrapers. Just my $0.63
The rest of the industry disagrees. Name a DRAM manufacturer working on disarg DRAM: I'll wait. Meanwhile everyone is working on 3D-DRAM as that could lead to a faster than Moore's "law" cost per bit scaling like we are seeing with NAND. As for the logic side both will be used. Advanced packaging for disagrigating parts that don't scale as well in addition to enabling designers to change out only some of the dies rather than doing a full chip tape-out like you would with a monolithic design just make sense. Regardless of your 0.63 cents whether you like it or not CFET will eventually come, and hopefully eventually we can do more than 2-device layer stacks. If logic can ever start stacking like NAND is right now, then everybody will need to start switching to the newest nodes again like they used to because otherwise they will never make a competitive product, and no amount of chiplets could ever change the fundamental cost per FET reality that comes with multi device layer nodes. Just looking at the excellent economics that CFETs might deliver, it is not hard to imagine how crazy that technology could be if it could be scaled up.

CFET.jpg

scaled_cell_SRAM.jpg

cost_comparisons.jpg
 
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Vertical inter-tier vias provide well documented thermal advantages.
Stacking many layers of logic does cause thermal issues, but again you want to balance design with objectives.

Cliff - funding information would be confidential and I would not be posting on a (semi)public site. ;-)
You can contact me directly at Chris@crossPORT.AI

A small scale FPGA implementation is already built and demonstrates 60mW per 100Gbps switched equivalency and latency of 40ns at 100Mhz.
 
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Here are a few other references one might want to look at to see detailed analysis of the thermal experiences of vertical interconnections.

The Development and Progress of Multi-Physics Simulation Design for TSV-Based 3D Integrated System - https://www.mdpi.com/2073-8994/15/2/418
Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs - https://www.mdpi.com/2079-9292/11/19/3013
High-Performance Logic-on-Memory Monolithic 3D IC Designs for Arm Cortex-A Processors - https://www.semanticscholar.org/pap...berg/5ac8bdc044192d15a3e92f400e0c379a79145fa6
 
With Micron having 232 layers in their memory chips, will the technologies Micron uses have value in semis in general or is strictly for memory? Will this technology be applied in chiplets? Will Micron make memory chiplets for others or will memory remain a largely a seperate component? Any input appreciated, Thanks
Arthur, I assume you are aware how 3D NAND is built? The fundamental insight is that the layers are not built with lithography. The base is built with lithography, the hundreds of layers cover the wafer with featureless uniform deposition, and then the layers are etched from top to bottom to create vertical columns of those layers, followed by various ALD steps which coat and fill the slits and wells to construct the dielectric and gate layers.

The enormous cost reduction occurs because of how cheap the layering is, and how it multiplies the value of the initial and final processing steps.

3D logic is not at all like that, since every layer is patterned. Even 3D DRAM is likely patterned at each layer. There is a vague similarity in how GAA ribbons start where the Si/SiGe layers begin as featureless uniform depositions which are then patterned and processed to open spaces around and within for the dielectrics and gates. Those initial layers, typically 6 of them, do have a multiplier effect though it is not nearly as momentus a cost reduction as the hundreds in the 3D NAND.

So, logic processes have borrowed a bit of inspiration from 3D NAND, but in most ways the processes are not compatible.
 
With Micron having 232 layers in their memory chips, will the technologies Micron uses have value in semis in general or is strictly for memory? Will this technology be applied in chiplets? Will Micron make memory chiplets for others or will memory remain a largely a seperate component? Any input appreciated, Thanks
3D NAND-like stacking works only because it's designed to fight near the storage market. It has a large access granularity(like 4~16kB), so you have little routing difficulties. Basically same thing everywhere. You can etch deep, deposit....etc creating ~100 layers of NAND cell at once and fill it with a channel material.

Also, 3D NAND works in us~ms scale since they use charge trapping to work(which is relatively slow compared to gates). So they can sustain various problems (channels getting narrower as it goes deeper...etc) of manufacturing. You don't really want to do this in fast logic chips.
 
The rest of the industry disagrees. Name a DRAM manufacturer working on disarg DRAM: I'll wait.
Just to be clear, the discussion is about extending the extra layers to logic chips building up vertically, and optionally to put other chiplets, perhaps a RAM chiplet, on top of the logic chiplet, correct?

Do you believe that thermal issues will get resolved in ways other than cheating (shutting down circuitry or slowing down the clocks)?

Are you suggesting exotic memory on the higher layers of the logic chip?
 
Arthur, I assume you are aware how 3D NAND is built? The fundamental insight is that the layers are not built with lithography. The base is built with lithography, the hundreds of layers cover the wafer with featureless uniform deposition, and then the layers are etched from top to bottom to create vertical columns of those layers, followed by various ALD steps which coat and fill the slits and wells to construct the dielectric and gate layers.

The enormous cost reduction occurs because of how cheap the layering is, and how it multiplies the value of the initial and final processing steps.

3D logic is not at all like that, since every layer is patterned. Even 3D DRAM is likely patterned at each layer. There is a vague similarity in how GAA ribbons start where the Si/SiGe layers begin as featureless uniform depositions which are then patterned and processed to open spaces around and within for the dielectrics and gates. Those initial layers, typically 6 of them, do have a multiplier effect though it is not nearly as momentus a cost reduction as the hundreds in the 3D NAND.

So, logic processes have borrowed a bit of inspiration from 3D NAND, but in most ways the processes are not compatible.
There are multiple approaches to 3D DRAM but the one getting the most attention at the device manufacturers has a stack of layers that are all patterned together. There is an approach where each layer is patterned and then they are bonded together but it is unlikely to be cost effective.
 
Micron layering nand is not unique to them. Every nand manufacturer does it and many of them are catching up to micron on the exact layer counts after falling behind a few years ago. This technology has no relevance to “chiplets” because 3D nand is done on a single wafer substrate, and unlike disagrigated designs (chiplets) 3D nand leads to a reduction in cost per fet. “Chiplets” is integrating multiple dies onto the same package via an organic interposer or interposer die. Meanwhile 3D nand is like building a skyscraper of transistors.

Is nand stacking realvent outside of nand flash? Probably, but probably not directly. DRAM is a transistor and a capacitor. Meanwhile nand is one transistor with two gates, so the same scheme cannot be applied for DRAM. This exact technology is also insufficient for logic because unlike nand and DRAM, logic is not just an array. The complex routing needed for logic is incompatible with how nand stacking is done. Furthermore because nand transistors are vertical nanowires, you cannot increase device performance without quickly reducing your transistor density. It is for these reasons that logic is moving to stacks of horizontal nanowires (note not stacked transistors but stacked nanowires on one common gate to get increased effective area at the same footprint) for the initial GAA nodes to get maximum performance per area.

TLDR nand stacking is an awesome technology that the memory guys came up with almost a decade ago when nand could shrink no further to enter a scaling era without any end in sight. Now that DRAM is hitting a wall (although nowhere near as hard as the nand flash wall) they are looking for a similar trick, although the exact solution will likely be very different to accommodate the unique particularities of DRAM. The more variable nature of logic/the need for logic to have good PPW characteristics will make multi layer devices harder to achieve than DRAM. But logic is farther from the scaling wall, and 2 transistor cfet stacks will further stave off the requirement for a more robust multi layer scheme.
YMTC uses 2 wafers and likely everyone will migrate to that approach eventually with logic on one wafer and the memory array on the other substrate.
 
Just to be clear, the discussion is about extending the extra layers to logic chips building up vertically, and optionally to put other chiplets, perhaps a RAM chiplet, on top of the logic chiplet, correct?

Do you believe that thermal issues will get resolved in ways other than cheating (shutting down circuitry or slowing down the clocks)?

Are you suggesting exotic memory on the higher layers of the logic chip?
This discussion was about if Micron's NAND stacking capabilities would revolutionize semis as a whole or just NAND flash. As for "ram chiplets" there is no such thing. There are RAM dies that can be packaged with other dies in a DIMM. They can also be put inside a 3D stack of DRAM dies (HBM). You can further stack these HBM dies onto an interposer of some kind to lower latency. Finally you can just stack the DRAM package(s) ontop of another logic package (think products like lakefield). None of these techniques is special or new though and has been done for years. All of these are also with regular DRAM dies in a slightly different package, rather than some special chiplet technology.

The industry would not be moving to CFET if there was a thermal runaway problem or a massive decrease in PPW. For this reason I have no reason to doubt the thermal issues are manageable for stacks of a few layers.

Already being done by just about everybody for years. As for what I was talking about: I was talking about if some CFET decendent or some parallel development could allow for stacking dozens rather than just 2 device layers like CFET, that would make ALL prior logic nodes irrelevant besides for things like power electronics. I wouldn't be surprised if doing so required some beyond CMOS technology. However my point was that if logic could ever find a cheat around device scaling like NAND did, then logic could enter a cost per FET scaling era comparable to what we saw in the 60s and 70s with the invention of the IC.

YMTC uses 2 wafers and likely everyone will migrate to that approach eventually with logic on one wafer and the memory array on the other substrate.
I don't recall seeing this technique being discussed by others, and to be honest I don't really understand the value prop since the array logic is already on the bottom for traditional NAND (imbedded in between the BOL). What benefit is there to breaking that device layer out onto another wafer and then bonding that to your wafer with your NAND? Seems like a more complicated way to have the same result.
 
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This discussion was about if Micron's NAND stacking capabilities would revolutionize semis as a whole or just NAND flash. As for "ram chiplets" there is no such thing. There are RAM dies that can be packaged with other dies in a DIMM. They can also be put inside a 3D stack of DRAM dies (HBM). You can further stack these HBM dies onto an interposer of some kind to lower latency. Finally you can just stack the DRAM package(s) ontop of another logic package (think products like lakefield). None of these techniques is special or new though and has been done for years. All of these are also with regular DRAM dies in a slightly different package, rather than some special chiplet technology.

The industry would not be moving to CFET if there was a thermal runaway problem or a massive decrease in PPW. For this reason I have no reason to doubt the thermal issues are manageable for stacks of a few layers.

Already being done by just about everybody for years. As for what I was talking about: I was talking about if some CFET decendent or some parallel development could allow for stacking dozens rather than just 2 device layers like CFET, that would make ALL prior logic nodes irrelevant besides for things like power electronics. I wouldn't be surprised if doing so required some beyond CMOS technology. However my point was that if logic could ever find a cheat around device scaling like NAND did, then logic could enter a cost per FET scaling era comparable to what we saw in the 60s and 70s with the invention of the IC.


I don't recall seeing this technique being discussed by others, and to be honest I don't really understand the value prop since the array logic is already on the bottom for traditional NAND (imbedded in between the BOL). What benefit is there to breaking that device layer out onto another wafer and then bonding that to your wafer with your NAND? Seems like a more complicated way to have the same result.
Stress management is a huge problem and also the yield is better. Not having the memory stack over logic makes stress management easier. Samsung showed it on their roadmap at IEDM a couple year ago. My belief is as we get above 500 layers everyone will go that way.
 
Just to be clear, the discussion is about extending the extra layers to logic chips building up vertically, and optionally to put other chiplets, perhaps a RAM chiplet, on top of the logic chiplet, correct?

Do you believe that thermal issues will get resolved in ways other than cheating (shutting down circuitry or slowing down the clocks)?

Are you suggesting exotic memory on the higher layers of the logic chip?
I understood that the question was if 3D designs being applied to memory could be applied to 'other' aspects - which would seem to be more than adding layers on top of logic chips. Thermal issues related to intensive logic circuitry (already having thermal issues) will obviously increase as these dies stack .. that much is readily apparant. Packaging has begun to introduce thermal separations for extracting heat in layered designs.

TSV and MIV vertical channels implemented in 3D stacking offer several methods of addressing thermal aspects without requiring a shut down of circuitry or slowing the clocks. You might want to read the papers I included above as they specifically deal with your question. There are cases where a TSV was used simply for cooling and nanofluids carried heat up (or down) through the layers and introduced cooling to the chipsets.

HBM is hardly super exotic these days. 3D designs can be seen to favour memory stacking as there are fewer' thermal challenges - its an 'easier' application. I am not sure it is fair to limit all possible implementations to a first win and then stop considering others.
 
YMTC uses 2 wafers and likely everyone will migrate to that approach eventually with logic on one wafer and the memory array on the other substrate.
Or, the rise of the machinery for BSPD will make it more attractive to build the logic process on the backside of the memory stack.
 
logic could enter a cost per FET scaling era comparable to what we saw in the 60s and 70s with the invention of the IC.
This could be arguably true, but the cost of the system (SIP, for example) is the important thing, and whatever you package shouldn't melt.

Cost: 2 years ago, moving from a 130um pad pitch to a 40um pad pitch was way too expensive for an ASIC. A major packaging company told me last year that only the big 4 foundries can handle packaging below 90um. That defines handling of 40um pitch dies as exotic IMO.

Thermal: More and more FETs getting stuffed into the die at faster frequencies. Keep in mind, most of the current used in logic is short circuit current that passes directly from the pmos through it's complementary nmos, instead of charging the fets of the next stage. The reason to go to the advanced logic processes is for speed. Thermally spreading out the surface area seems obvious to me, and also provides more pads for BOW (bunch of wires). Note, I am comparing 2D vs 3D packaging and using an interposer of a sub 500nm pitch, for example.

I am questioning the practicality of 3D on logic ASICs (not standard, off the shelf parts from Intel, AMD, etc), whether within the die or stacked dies. I like Mr. Ng's optimism. Perhaps the industry will pump oil through the SIP?
 
This could be arguably true, but the cost of the system (SIP, for example) is the important thing, and whatever you package shouldn't melt.

Cost: 2 years ago, moving from a 130um pad pitch to a 40um pad pitch was way too expensive for an ASIC. A major packaging company told me last year that only the big 4 foundries can handle packaging below 90um. That defines handling of 40um pitch dies as exotic IMO.

Thermal: More and more FETs getting stuffed into the die at faster frequencies. Keep in mind, most of the current used in logic is short circuit current that passes directly from the pmos through it's complementary nmos, instead of charging the fets of the next stage. The reason to go to the advanced logic processes is for speed. Thermally spreading out the surface area seems obvious to me, and also provides more pads for BOW (bunch of wires). Note, I am comparing 2D vs 3D packaging and using an interposer of a sub 500nm pitch, for example.
We shall see. This sort of stuff is way too far in the future to make definitive statements. Regardless if logic 3D stops with CFET or if it continues growing up and up, I think disag will still have a place.

I am questioning the practicality of 3D on logic ASICs (not standard, off the shelf parts from Intel, AMD, etc), whether within the die or stacked dies. I like Mr. Ng's optimism. Perhaps the industry will pump oil through the SIP?
That's all well and good I suppose. But let's say in like the 2040s or something we can get like 32L nodes. Even if we assume this has to be done with sequential CFET (or something similarly expensive), the cost per wafer would have gone up by 6.2x while density would have gone up by 1.5x*15x = 22.5x. This would lead to a cost per device plummeting to 28% of what it was. With that much transistor real-estate available to designers, couldn't general purpose designs have their own on board ASICs. Heck if you gave it a few more gens of stacking, that general purpose design might just be faster than some ASICs built on pre stacking nodes via brute force alone. Obviously there are tons of issues to solve before you can get there, but I think it illustrates my point of how disruptive this technology could be if the logic guys could find a way to scale like that.

While we hopefully wait for the arrival of 3D DRAM and logic, we will just have to content ourselves with the price per bit for NAND flash plummeting every few years.
 
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