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Does increased design cost per node assume an increase in the number of transistors? How to guesstimate design costs for die shrinks?

jms_embedded

Active member
Handel Jones at IBS was cited in this 2018 article Big Trouble at 3nm with the following graph of skyrocketing design costs.

nano3.png

I graphed these numbers on a log-log plot and did a linear fit:
designcostpernode1.png

Does anyone have a sense of whether the assumption is for constant die area (more transistors at advanced nodes) or constant transistor count (die shrinks) --- I'm guessing it's the former. If someone's doing a die shrink from node N to node N+1, does the design cost increase much?
 
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