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DFT is not technology dependent in terms of much beyond standard device scaling. Devices get smaller, so you can pack more gates in, but they also tend to have worse leakage current as we scale down. DFT is just the insertion of additional logic/sequential elements for testing. As with scaling normally, we can test a little bit faster as well by having smaller devices and better DFT design.
We use slower test chains because for one, it relaxes the design requirements on the DFT components which allows us to 1) be more confident that adding DFT won't kill other timing/power specs for the live design components, and 2) we can't always hook a tester up to it that can go fast enough, as you address in your question.
Power can be a limiting factor when testing massive numbers of parts in parallel - you need a tester which can handle the thermal implications as well as power delivery. This is a gating factor for some kinds of ICs, but not all.