Chip-Making Juggernaut TSMC Eyes Multibillion-Dollar Arizona Factory Expansion

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16/12 is on the linear cost curve and have more advantages over just having small transistors as I have stated above

could you clarify what you mean by "linear cost curve"? (I have a guess but not 100% sure)

 

[cliff]

The cost per FET. There were some excellent charts that compared the prices. We taped out last year on both ts40nm and ts12ffc. I think 12ffc is worth it and it is our focus.

I wish TSMC would add a DUV machine in Phoenix. I don't think EUV will be practical for ASICs for awhile, but TSMC would know better. I am just a user.

 

[benb]

The cost per FET. There were some excellent charts that compared the prices. We taped out last year on both ts40nm and ts12ffc. I think 12ffc is worth it and it is our focus.

I wish TSMC would add a DUV machine in Phoenix. I don't think EUV will be practical for ASICs for awhile, but TSMC would know better. I am just a user.

N3 fabs will have 193 and 13.5 nm litho. this is because each node builds on the next. The BEOL, copper wiring, doesn't change, even though the features underneath get smaller. The wiring will use some 13.5, the first layers. Then the rest is 193 up to 10s of microns wide lines (bus lines).

 

[cliff]

Good point. You are correct. The will have the DUV machines for layers above the EUV layers. They just choose to construct the FETs, etc with the EUV. Perhaps they can produce 16nm with those DUV machines, depending on the EUV and China situation

 

[nghanayem]

Good point. You are correct. The will have the DUV machines for layers above the EUV layers. They just choose to construct the FETs, etc with the EUV. Perhaps they can produce 16nm with those DUV machines, depending on the EUV and China situation

N16 doesn't use EUV at all. Only some of the N7 versions use it (N7+ and N6), as well as the later nodes.

 

[Fred Chen]

The cost per FET. There were some excellent charts that compared the prices. We taped out last year on both ts40nm and ts12ffc. I think 12ffc is worth it and it is our focus.

I wish TSMC would add a DUV machine in Phoenix. I don't think EUV will be practical for ASICs for awhile, but TSMC would know better. I am just a user.

There's always Intel 16.

 

[cliff]

N16 doesn't use EUV at all. Only some of the N7 versions use it (N7+ and N6), as well as the later nodes.

I know.

"There's always Intel16"... Yes. My whole point is that we need to add a second (or 3rd) source. Most ASIC customers will probably not be able to afford or access the EUV processes. It isn't easy to automate process that fights physics. You run into non-obvious rules.

 

[benb]

Some predictions: Given 6 fab shells in AZ and TSMC habit (not always practiced in recessions) of building a fab every 6 months, and having 4 major clusters (Hsinchu, Tainan, Taichung, and now AZ), we should expect equipment-move-in every 2 years in AZ. If phase 1 is complete in 2024, phase 2 would be 2026, phase 3 2028, phase 4 2030, phase 5 in 2032, then phase 6 in 2034.

Risks in this prediction: It looks like it will be faster than this, much faster. The fact that all six are in stages of construction at once today suggests AZ may see more investment than the other 3 clusters. I think Hsinchu and Tainan science parks may be full. Taichung is newer and has room, like AZ. So at a 1 fab/year pace, split between Taichung and AZ, AZ phase 6 may be complete by 2030. With the late 2020s being very busy and ramping a new fab every year.

 

[cliff]

Thanks Ben. Do you (or anybody) have a prediction on TSMC's interposer capability in AZ? For example, flipchipping onto an interposer with HBM2/3 probably needs to be done at a foundry (I called Amkor. They referred me to the foundries below 90nm). We can't design for just the SOC anymore. I suspect the neanderthal processes will be specializing in interposers with TSVs

 

[nghanayem]

Thanks Ben. Do you (or anybody) have a prediction on TSMC's interposer capability in AZ? For example, flipchipping onto an interposer with HBM2/3 probably needs to be done at a foundry (I called Amkor. They referred me to the foundries below 90nm). We can't design for just the SOC anymore. I suspect the neanderthal processes will be specializing in interposers with TSVs

Presumably none. Packaging is done at separate facilities from fabs. It is also more labor intensive, thus expensive to do in the USA compared to a fab where labor is a relatively small cost.

Also you might have better luck finding packing suppliers with the query "hybrid bonding". This is the more common name for interposers with TSVs.

 

[Paul2]

I have no doubt TSMC will continue to invest outside of Taiwan. It is a very calculated geopolitical move and I know for a fact TSMC can make it work financially. Mark my words on this one.

TSMC N3 will be the last big FinFET node so there will be huge demand for years to come. Brining N3 to the US makes perfect sense. Let's see what TSMC has to say on their next investor call and where the 2023 CAPEX will be spent.

Globalfoundries spent billions of dollars trying to compete with TSMC to no avail. Samsung has spent hundreds of billions of dollars trying to compete with TSMC to no avail. Intel really is our last hope at having a competitive foundry landscape and I think they can do it, but it all depends on Intel 18A. If 18A is a competitive node I think IFS has a chance at landing some big customers, absolutely.

Exciting times for sure........

Intel can't for a simple reason that their volumes are nowhere near. Which itself will mean they will have to cater to tons of small clients, and that will eat the profit.

 

[nghanayem]

Intel can't for a simple reason that their volumes are nowhere near. Which itself will mean they will have to cater to tons of small clients, and that will eat the profit.

I think it is worth considering that all of intel's CPUs going forward are tiny little compute dies. And that 18A is not supposed to enter HVM until the end of 2024. By then intel will have far more EUV tools to equip their large number of fabs: also remember a couple years ago intel's leading edge capacity was not that much smaller than TSMC's leading edge capacity (as opposed to overall capacity where intel was much smaller). intel also has the benefit of any fabs running 20A can quickly and seamlessly transfer to 18A. There should be more than enough capacity for intel to be a second or third source for ARM SOC makers and the like, as I would. Personally I don't think that folks like Qualcomm or MediaTek will commit to exclusively or primary sourcing intel. I think they would want to test the waters because 18A is still an unknown quantity, and capacity needs to be planned far in advance. But if intel executes than I don't see why they can't become the primary supplier beyond "2nm" for companies that aren't bound to TSMC by the hip.