China’s top chipmaker will ‘struggle’ to make cutting-edge chips competitively

[Daniel Nenni]

KEY POINTS

• -China’s largest chipmaker SMIC won’t be able to produce cutting-edge chips competitively if it continues to be cut off from advanced equipment, analysts told CNBC.
• -SMIC has been the target of U.S. sanctions since 2020 when it was put on an U.S. trade blacklist restricting its access to certain technology.
• -It has been unable to obtain the extreme ultraviolet lithography machines which only Dutch firm ASML is currently capable of making.
• -But with SMIC being the key to China’s chip ambitions, analysts expect the government to step up support for the chipmaker.
  
  
  China’s largest chipmaker SMIC won’t be able to produce cutting-edge chips competitively if it continues to be cut off from advanced equipment, analysts told CNBC.
  
  China’s largest chipmaker SMIC won’t be able to produce cutting-edge chips competitively if it continues to be cut off from advanced equipment, analysts told CNBC.
  
  State-backed SMIC, or Semiconductor Manufacturing International Co., is making 7-nanometer semiconductor chips, placing it in the league of Intel and others.
  
  However, SMIC has been the target of U.S. sanctions since 2020 when it was put on a U.S. trade blacklist which restricts its access to certain technology. It has also been unable to obtain the extreme ultraviolet (EUV) lithography machines — which only Dutch firm ASML is capable of making.
  
  Without EUV machines, the Chinese tech giant is not able to produce the high-tech semiconductors on a large scale at lower costs.
• 
  
  
  
  
  China is behind in its ability to design and produce advanced chips, says Chris Miller, author of “Chip War”
  
  “It’s just not commercially profitable for SMIC to make those chips with less advanced equipment,” said Phelix Lee, equity analyst for Morningstar Asia.
  
  Following the 2020 sanctions, the U.S. last year introduced sweeping export restrictions aimed at cutting China off from advanced chip tech and equipment. Washington is concerned that China could use these advanced semiconductors in artificial intelligence and military applications.
  
  The U.S. has sought support from other key chipmaking nations including South Korea, Japan and the Netherlands. The Netherlands as well as Japan have reportedly followed the U.S. in imposing rules aimed at restricting China from accessing advanced chip tech.
  
  According to Dutch regulations, ASML will need to apply for a license to export its EUV machines. ASML has not exported the highly complex machines to China so far.
  
  “Can SMIC produce in a commercially viable way scaled by the hundreds of thousands or tens of millions in some cases? That’s what the most advanced tools let you do,” Chris Miller, author of “Chip War” told CNBC.
  
  SMIC did not respond to CNBC’s request for comment.
  
  Competitive landscape
  The world’s most advanced chip facilities — such as Taiwan Semiconductor Manufacturing Company and South Korean electronics giant Samsung — rely on tools from just a small number of companies largely in the U.S., Japan and the Netherlands.
• 
  TSMC and Samsung began mass producing 7-nanometer chips in 2018. Both firms use ASML’s EUV machines.
  
  “Nanometer” in chips refers to the size of individual transistors on a chip. The smaller the size of the transistor, the more of them can be packed onto a single semiconductor. As such, smaller nanometer sizes typically yield more powerful and efficient chips.
  Both companies have a roadmap to produce 2-nanometer chips in 2025. Samsung will begin making 1.4-nanometer chips in 2027. Both companies started mass production of 3-nanometer chips last year.
• 
  
• Still lagging behind
  SMIC is still generations behind TSMC and Samsung. Without advanced chip-making machines, SMIC is going to fall further behind.
• 
  “So far I don’t see domestic players being able to provide those machines to SMIC,” said Morningstar’s Lee.
  At least for the next couple of years, SMIC is going to struggle to produce chips that are as effective and as high quality as those that are produced abroad.
  
  While some Chinese firms are trying to build equivalent tools domestically, they remain fairly far behind, said Miller.
  In February, ASML said that a former employee in China had stolen data about its proprietary technology.
• 
  “It will likely take some time before China begins to replicate the capabilities that these important tools have,” said Chris Miller, who is also an international history professor at Tufts University.
• 
  “At least for the next couple of years, SMIC is going to struggle to produce chips that are as effective and as high quality as those that are produced abroad,” the professor said.
• 
  
  
  
  
  SMIC has a long way to go in catching up with TSMC, says analyst
  
  Lee said it is “quite unlikely, at least in the next five years” for SMIC to be able to produce the latest generation of chips such as 5 or 3-nanometer chips. “If we want to close the gap [between SMIC and TSMC], we should be looking at a 10-year horizon,” said Lee.
• 
  China wants tech progress
  But with SMIC being the key to China’s chip ambitions, analysts expect the government to step up support for the chipmaker. SMIC already benefits from government subsidies and state-backed research projects.
• 
  “I see a lot of financing to happen for SMIC. These can come from bank loans, issuing new shares, or setting up operating companies with the help of government funding,” said Lee.
• 
  The Chinese government has made it clear they want to get as close as possible to the cutting edge...
  
  In its five-year development plan, China said it would increase research and development spending by more than 7% per year between 2021 and 2025, in pursuit of “major breakthroughs” in technology and self-reliance.
• 
  Domestic tech giants from Alibaba to Baidu have been designing their own chips, seen as a step toward China’s goal of boosting its domestic capabilities in chip tech.
• 
  “The Chinese government has made it clear they want to get as close as possible to the cutting edge and so a lot of the funds will be devoted towards trying to produce close to cutting edge chips,” said Miller.
• 
  “SMIC is going to benefit from a new level of support from the Chinese government which doesn’t want to see it fail and wants to see it, if possible, continue to make progress technologically,” he added.

 

[Fred Chen]

As a logic foundry, Semiconductor Manufacturing International Corp is only supporting down to 28nm, but as a flash foundry, it supports down to 45nm NOR and 24nm NAND, with GigaDevice Semiconductor Inc. as the likely customer (competition concern mainly for Winbond and Macronix). In other words, it does not appear to be SMIC's charter presently to be active in the same sector as TSMC. However, Huawei has brought up 14 nm self-sustenance and 24 nm fin pitch (N3) has been published at CSTIC, so it looks like someone else other than SMIC could be playing.

 

[benb]

According to Ray Dalio's latest LinkedIn post, China is embarking on a new economic system.

What I Think Is Going On 1) with China-US Relations, 2) with Their Relations with Other Countries, and 3) in China

In my last post, I described the big cycle template, consisting of the five major forces. Today’s post is the follow-up I promised, focusing on the great power conflict and what’s going on with China.

www.linkedin.com

"The economy is now much more a command economy—e.g., each province has been given growth targets that they must hit, and if they don’t have adequate funding, it will be financed by special-purpose bonds."

If this is true, and applies to semiconductor equipment, then we should expect new organizations, tied to provinces, and perhaps the military, with great secrecy, procuring EUV lithography equipment.

 

[ta152h]

Have Nikon and Canon completely given up on EUV machines, or BEUV? I can't believe fab companies can be too comfortable with just one source, but by all indications ASML will be the only game in town.

 

[Fred Chen]

If you really want to depend on EUV, but don't have enough EUV systems, then you need to take Intel's chiplet approach as in Meteor Lake, relying heavily on TSMC.

Why get into this position, though.

 

[ta152h]

If you really want to depend on EUV, but don't have enough EUV systems, then you need to take Intel's chiplet approach as in Meteor Lake, relying heavily on TSMC.

Why get into this position, though.

Intel was using TSMC even before moving to their EUV nodes. Intel makes their nodes primarily for CPUs, not GPUs, and obviously the characteristics are different. Certainly Intel 7 would be a poor choice for a GPU, and it's pretty clear I4 would be too, not having high density libraries. So, irrespective of EUV, it seems Intel made an easy decision.

In any case, I4 is just getting their feet wet with EUV, and given how limited their production will be (most of the chiplets are made on less dense nodes), it's not clear they are being limited. Yet. I3 is a completely different story though, especially since they should have some outside customers using it.

 

[Paul2]

The question in not whether they can make it competitively, but whether they can do it economically.
As of now, they already have preferential tax regime, which amounts to a subsidy. We don't know what other subsidies they enjoy.

If they can do few year old nodes close to market rate, with subsidy pulling them out, they keep going, and continue improving. If the govt cannot do much but fund them fabbing chips at double digit loss for years, they will likely put a lid.

BOE been in the red for more than a decade (15 years, if I recall correctly?), being constantly bailed out by government funds. I think they will treat SMIC far more favourably than BOE. And SMIC been in black for quite a while already, so it's already doing better than BOE of 201X.

 

[Fred Chen]

Intel was using TSMC even before moving to their EUV nodes. Intel makes their nodes primarily for CPUs, not GPUs, and obviously the characteristics are different. Certainly Intel 7 would be a poor choice for a GPU, and it's pretty clear I4 would be too, not having high density libraries. So, irrespective of EUV, it seems Intel made an easy decision.

In any case, I4 is just getting their feet wet with EUV, and given how limited their production will be (most of the chiplets are made on less dense nodes), it's not clear they are being limited. Yet. I3 is a completely different story though, especially since they should have some outside customers using it.

It's a bit different here, since they can't ship Meteor Lake without TSMC. Even 18A will have TSMC participation wherever there's an Intel CPU. At least with Intel 7 they had their independence. Being a TSMC customer, you have to pay to reserve the capacity. All for the sake of using EUV, which still can't shake multipatterning off?

 

[ta152h]

It's a bit different here, since they can't ship Meteor Lake without TSMC. Even 18A will have TSMC participation wherever there's an Intel CPU. At least with Intel 7 they had their independence. Being a TSMC customer, you have to pay to reserve the capacity. All for the sake of using EUV, which still can't shake multipatterning off?

OK, so that's one way of looking at it. But, let's look at it a reverse way.

There is no way to make a single node work optimally for GPUs and CPUs; each prefer different prioritizations as one is a largely parallel, the other more serial.

Intel clearly prioritizes CPUs, as given their never ending superiority in clock speeds. TSMC tends to be more balanced, but that is at least part of why AMD can't reach the clock speeds Intel processors do. A monolithic chip has to simple accept these tradeoffs, with a relatively poor or expensive GPU, or both, attached to the CPU. It's not that bad for desktops, because it's unusual to buy a desktop and really care too much about the iGPU; if you do care about the GPU, you buy a discrete card, if you don't, it's fine. Notebooks are different, as the discrete GPU attach rate is a lot lower, and the costs and compromises in getting one a bit more daunting. Certainly you can, but having a solid GPU with the processor avoids that expense, not only in money, but also in size of the motherboard, and the complexity of it. Plus, discrete cards in mobile simply do not even approach the advantages of those in desktop machines, due to cooling limitations, power limitations, and space limitations.

So, now you can use processes better aligned with your goals. A very high performance node for the processor, and a node with a focus more on density and power use for the GPU.

Let's take this one step further though, and then look at gaming consoles. I'd bet real money that Intel is going to be very aggressive in going after them, given all their advantages. If you're a console maker and you've been limited by production of processors, would you rather have Intel, which makes their own, or AMD which can not and has been severely limited in the past by their inability to make enough product. Not that this hasn't, or can't happen to Intel, but they certainly have more control over it.

And, right now, given all that Intel has on its plate, staying with TSMC makes sense, at least for mobile. They've got experience with it, and Battlemage will be using it as well. But, there's nothing to prevent Intel from making GPUs on their own fabs, and I think the likelihood rises as we look towards 18A. Since Intel can't sell their crazy performance nodes to fab customers on a large scale, they are going to need nodes that focus more on density and power use. Or they'd better just shut down IFS, because their number of customers will be really small.

Looking at it yet another way, can Intel really hope to get any companies making GPUs to try their fabs, if they won't use them for the same purpose? That sure would be a difficult sale.

So, I think it's a temporary situation. Maybe it won't change soon, or maybe it will. I think the latter, but it's not a permanent and/or immutable situation.

 

[blueone]

OK, so that's one way of looking at it. But, let's look at it a reverse way.

There is no way to make a single node work optimally for GPUs and CPUs; each prefer different prioritizations as one is a largely parallel, the other more serial.

Intel clearly prioritizes CPUs, as given their never ending superiority in clock speeds. TSMC tends to be more balanced, but that is at least part of why AMD can't reach the clock speeds Intel processors do. A monolithic chip has to simple accept these tradeoffs, with a relatively poor or expensive GPU, or both, attached to the CPU. It's not that bad for desktops, because it's unusual to buy a desktop and really care too much about the iGPU; if you do care about the GPU, you buy a discrete card, if you don't, it's fine. Notebooks are different, as the discrete GPU attach rate is a lot lower, and the costs and compromises in getting one a bit more daunting. Certainly you can, but having a solid GPU with the processor avoids that expense, not only in money, but also in size of the motherboard, and the complexity of it. Plus, discrete cards in mobile simply do not even approach the advantages of those in desktop machines, due to cooling limitations, power limitations, and space limitations.

So, now you can use processes better aligned with your goals. A very high performance node for the processor, and a node with a focus more on density and power use for the GPU.

Let's take this one step further though, and then look at gaming consoles. I'd bet real money that Intel is going to be very aggressive in going after them, given all their advantages. If you're a console maker and you've been limited by production of processors, would you rather have Intel, which makes their own, or AMD which can not and has been severely limited in the past by their inability to make enough product. Not that this hasn't, or can't happen to Intel, but they certainly have more control over it.

And, right now, given all that Intel has on its plate, staying with TSMC makes sense, at least for mobile. They've got experience with it, and Battlemage will be using it as well. But, there's nothing to prevent Intel from making GPUs on their own fabs, and I think the likelihood rises as we look towards 18A. Since Intel can't sell their crazy performance nodes to fab customers on a large scale, they are going to need nodes that focus more on density and power use. Or they'd better just shut down IFS, because their number of customers will be really small.

Looking at it yet another way, can Intel really hope to get any companies making GPUs to try their fabs, if they won't use them for the same purpose? That sure would be a difficult sale.

So, I think it's a temporary situation. Maybe it won't change soon, or maybe it will. I think the latter, but it's not a permanent and/or immutable situation.

I hope you're wrong about Intel, because if IFS doesn't succeed they're well on their way to becoming the next IBM. Shrinking in relevance and becoming a shadow of its former self. My sense is that Gelsinger will do whatever is necessary to make IFS a success. His entire reputation and ego are riding on it. I don't know if they'll succeed, and I haven't agreed with many of Gelsinger's decisions in the past, but I can't think of a more motivated CEO at the moment, save perhaps Elon Musk.

 

[cliff]

Intel clearly prioritizes CPUs, as given their never ending superiority in clock speeds. TSMC tends to be more balanced

So you think that determination of clock speeds has to do with the foundry at the same'ish process nodes? Interesting. Perhaps it is due to willingness to put lots of labor to fine tune the problematic datapaths (timing closer). Perhaps it is a power/performance/area/cost tradoff? Perhaps it is decisions of going with a larger die rather than chiplets (yield vs cost vs heat dissipation, vs ...). What does this have to do with TSMC?

 

[cliff]

My sense is that Gelsinger will do whatever is necessary to make IFS a success

... and post his design rules (you can even withhold your model files) and start MPW services so that us EDA/IP provider companies can get moving on your processes.

 

[nghanayem]

All for the sake of using EUV, which still can't shake multipatterning off?

I doubt it will come back, but I wonder if at some point some folks will go back to SAQP instead of pushing to the pitch limits of SALELE. I have to imagine it is cheaper, albeit it is probably much harder to pull off.

 

[cliff]

I wonder too.

Fred and Mr Ng, in your opinions, can you guys speculate the difference is yields and throughput on single patterning (SALELE, correct?) vs double patterning (layers 1-4)? Use a 100 sqmm die for example, or whatever size you are best able to estimate. Assume a full layer stack. I am really looking for both NRE (mask) costs and recurrent (wafer) costs.

Anybody on this forum want to speculate on single vs double patterning on the EUV layers?

The followup question will be DUV double patterning vs EUV single patterning.

 

[nghanayem]

I wonder too.

Fred and Mr Ng, in your opinions, can you guys speculate the difference is yields and throughput on single patterning (SALELE, correct?) vs double patterning (layers 1-4)? Use a 100 sqmm die for example, or whatever size you are best able to estimate. Assume a full layer stack. I am really looking for both NRE (mask) costs and recurrent (wafer) costs.

Anybody on this forum want to speculate on single vs double patterning on the EUV layers?

The followup question will be DUV double patterning vs EUV single patterning.

SALELE is EUV double. Fred wrote up a good article on it that I would recommend. Cost wise I've seen it thrown around in whitepapers that EUV direct print is more expensive than DUV LELE or SADP, and less than DUV SAQP or LELELELE.

As for EUV direct print vs EUV SALELE, LELE, or SADP, I would assume that the cost difference would be similar (maybe a bit smaller) to what the cost adder is for DUV single vs double.

Yield is a product dependent metric and isn't useful when discussing process integration decisions (IMO). For these kinds of decision you would want to compare defect densities for iso features. For example you wouldn't compare defect densities of scheme A on the 5LPE HD cell vs scheme B for the 5LPE UHD cell as these aren't apple's to apple's comparisons and will skew your data to make scheme B look worse than it otherwise would.

As for how complex multipatterning impacts DD, just look at the intel 4 whitepaper from last year. Going from i7 to i4 would have been a 30% mask count increase, but going to EUV on the relevant layers caused a 20% reduction from i7 (a 38% mask count reduction from EUV-les i4). Multiply the EPE of all of those extra litho steps plus any defects created in all of those extra steps required just to make the pattern you want for SAQP/LE^x and yeah EUV is a big DD reducer over a MP scheme with comparable resolution. In the case of SAQP you also need to have very good process control to lock down pitch walking (Fred also wrote a wonderful article on SAQP that explained how this works to me so go check it out if you want all of the nitty gritty details). If memory serves from that same article you are also restricted to only having odd numbers of metal tracks or something like that.

 

[cliff]

SALELE is EUV double. Fred wrote up a good article on it that I would recommend. Cost wise I've seen it thrown around in whitepapers that EUV direct print is more expensive than DUV LELE or SADP, and less than DUV SAQP or LELELELE.

As for EUV direct print vs EUV SALELE, LELE, or SADP, I would assume that the cost difference would be similar (maybe a bit smaller) to what the cost adder is for DUV single vs double.

Yield is a product dependent metric and isn't useful when discussing process integration decisions (IMO). For these kinds of decision you would want to compare defect densities for iso features. For example you wouldn't compare defect densities of scheme A on the 5LPE HD cell vs scheme B for the 5LPE UHD cell as these aren't apple's to apple's comparisons and will skew your data to make scheme B look worse than it otherwise would.

As for how complex multipatterning impacts DD, just look at the intel 4 whitepaper from last year. Going from i7 to i4 would have been a 30% mask count increase, but going to EUV on the relevant layers caused a 20% reduction from i7 (a 38% mask count reduction from EUV-les i4). Multiply the EPE of all of those extra litho steps plus any defects created in all of those extra steps required just to make the pattern you want for SAQP/LE^x and yeah EUV is a big DD reducer over MP. In the case of SAQP you also need to have very good process control to lock down pitch walking (Fred also wrote a wonderful article on SAQP that explained how this works to me so go check it out if you want all of the nitty gritty details). If memory serves from that same article you are also restricted to only having odd numbers of metal tracks or something like that.

Thanks Mr. Ng! I misinterpreted this article: https://resources.sw.siemens.com/en...-multi-patterning-at-5nm-sadp-saqp-and-salele "self-aligned double and quadruple patterning (SADP, SAQP) and self-aligned litho-etch litho-etch (SALELE), have become a necessity at advanced IC design process nodes". Actually, I seem to misinterpret almost everything you process guys say. For example, I use the MKS system. You guys use the FNS (foundry numbering system). I added the new words LELE, LELELE, and LELELELE to my dictionary. Maybe @mozartct can write a paper on the history of FNS and Intelese/Intelish.

I am just trying to figure out what we are willing to migrate customers to in the future. We automate double patterning and have no intention of doing quadruple patterning. LELELELE for your foundry types. I penciled in N6 based on your input a few months ago. I assumed that is double patterned (LELE'ed, or that other 4 letter word).

The number of tracks of the foundry cells doesn't matter to us. We make our own cells for process migration reasons. Customers can use the foundry cells with their odd tracks, I guess. I still question the utilization %.

Every once in a while, I gotta see what you crazy guys are doing. I will head back to my decade now...

 

[nghanayem]

Actually, I seem to misinterpret almost everything you process guys say. For example, I use the MKS system. You guys use the FNS (foundry numbering system). I added the new words LELE, LELELE, and LELELELE to my dictionary. Maybe @mozartct can write a paper on the history of FNS and Intelese/Intelish.

What you refer to intelese is a marketing name that makes it easier to convey the capabilities of the node vs prior versions rather than the process number. We don't use MKS because it is not a good indicator for what new process technologies offer. Using gate pitch as your metric N3 would be called 17nm if we set 90nm as the baseline. Yet N3 is something on the order of 98x the chip density of 90nm and WAY better PPW. 17nm sounds hardly descriptive of N3's improvements. So unless you want to have some number or name scale that is tied to certain density ranges calculated with ARM A7 area or the Bohr metric you can't really capture real density improvements offered by new nodes. And even if you do that you ignore the PP part of PPAC. 20nm to 16FF there was a small realized density boost, basically no theoretical density boost, a 50% freq bump, and a 60% power reduction. Boosts like that deserve to be recognized, and might even give a big shrink by being able to get away with denser routing/HD cells and still getting a big performance per watt improvement.

Long story short I couldn't give you a x nm name for a node. They are all different from each other with different design points and trade-offs. I can compare individual features, but coming up with one all encompassing number to represent everything is a much harder task with no real solution given the varying needs of different customers. HPC customers may say N4X is a better node than N3. Meanwhile Apple would never consider using N4X for their A-series over N3, N3E, or even N4P.

I am just trying to figure out what we are willing to migrate customers to in the future. We automate double patterning and have no intention of doing quadruple patterning. LELELELE for your foundry types. I penciled in N6 based on your input a few months ago. I assumed that is double patterned (LELE'ed, or that other 4 letter word).

N6 has SAQP for the fins. N5 does as well, so presumably for this specific application it is easy enough that SAQP is more desirable than EUV SALELE.

The number of tracks of the foundry cells doesn't matter to us. We make our own cells for process migration reasons. Customers can use the foundry cells with their odd tracks, I guess. I still question the utilization %.

Even your custom logic would be limited to this limitation due to how pitch splitting works. Obviously this and being restricted to unidirectional lines are not issues when you use LELE, LELELE, etc. However those approaches are more expensive than SADP and SAQP.

Every once in a while, I gotta see what you crazy guys are doing. I will head back to my decade now...

Come again!

 

[ta152h]

So you think that determination of clock speeds has to do with the foundry at the same'ish process nodes? Interesting. Perhaps it is due to willingness to put lots of labor to fine tune the problematic datapaths (timing closer). Perhaps it is a power/performance/area/cost tradoff? Perhaps it is decisions of going with a larger die rather than chiplets (yield vs cost vs heat dissipation, vs ...). What does this have to do with TSMC?

Some of what you are saying is strange, because it's essentially repeating what I said. So, yeah, we agree on most of it.

Let's start with what we agree on, and what I stated earlier. Intel prioritizes clock speed over density and power usage. Completely agree. That was my point, that's fine for a desktop CPU, but not really good for a GPU. At all. That's my point about TSMC. They are better for what Intel needs with their GPUs, and being able to make it there gives their GPUs a boost, compared to what they would be capable of on their own nodes. Their own nodes might have a bit more clock speed, but it's almost trivial when you consider the tradeoffs in density and power use. Now they can get the best of both worlds.

Intel has had the highest clocked processors, at least compared to TSMC, I think forever. Yes, clock speed is a combination of architecture and process, so we can't say for sure. But, it's pretty close. Because you don't think AMD looks at speed paths and optimizes for them? Or they don't know how to make a high speed architecture? Look at Bulldozer, it was definitely a speed king, and definitely not a brainiac. I don't think they forgot how.

But, here's the reality, what we know. Intel makes the highest performing processor, based on single-threaded performance. This is the holy grail in computing, and the most difficult to advance. This despite it being a node "behind" the one AMD is making Ryzen 4 on. Forgetting IPC, because that is purely architecture, why does every generation of Intel processor clock higher? I mean, it's not even close now, just look at the overclocking records, no one even would consider an AMD.

So, yeah, it's pretty clear Intel is better, even a node behind, at that metric, because that just happens to be what they care most about. AMD does everything they can to improve single-threaded performance as well, including architecting the processor for good clock speeds, and eliminating bottlenecks to it; that's not just an Intel thing. But, given AMD is always behind (and so is every other processor made at TSMC), and not by a little, and given AMD has not too long ago made very high clock speed processors (which lost some clock speed when moving from 32nm to later nodes, which used higher density libraries), I don't think it's super likely this is just architecture based, and that Intel is more optimized for clock speed. It might be as well, but most of the clock speed gains Intel got on their 10nm family were from optimizations to the process, and the same could be said for 14nm.

Now if they resurrect the Pentium 4

 

[ta152h]

I hope you're wrong about Intel, because if IFS doesn't succeed they're well on their way to becoming the next IBM. Shrinking in relevance and becoming a shadow of its former self. My sense is that Gelsinger will do whatever is necessary to make IFS a success. His entire reputation and ego are riding on it. I don't know if they'll succeed, and I haven't agreed with many of Gelsinger's decisions in the past, but I can't think of a more motivated CEO at the moment, save perhaps Elon Musk.

I think somehow the message I was trying to say wasn't the message you received.

I think they will be successful with IFS, and I think the in future they will have nodes more suitable for GPUs, and other less performance intense scenarios. But, right now, if you're making a GPU, you'd be crazy to make it on I7 compared to a TSMC node. It would be horrible at the same size and power envelope. And how will they sell these nodes to customers, when they clearly aren't ideal for most usage scenarios. That's why I think Intel will need to priority density and power use much more in at least some of their nodes. I can't see it working any other way, and Pat Gelsinger knows a lot more than I ever will, and clearly knows this too.

I agree about Gelsinger. IFS is his legacy. The winning architectures they have now (Alder Lake, for example) were in development long before he came. His pivoting so strongly to IFS will define whether he's a success or failure, because he gave up a lot of parts of the business to have the money for it. Not to mention Tower.

I think your views on IBM are a bit severe. Don't get me wrong, no three companies combined are as dominant as IBM was, but for exactly that reason I think it was unsustainable. But, almost every year they are the leaders in patents, and their mainframes are still the backbone of businesses everywhere. They just aren't visible. But, they don't like commodity businesses, so leave them. But, let's see how good their IP they sold to the Japanese company is, and also how well they do in Quantum computing. Of course, the Red Hat purchase is working out well, and growing strongly, but do we give them any credit for that? I don't, although they have managed it well, and it's growing very well since they bought it. Their history is typically buying companies and watching them die. But, they sure make a lot of money, and although they aren't always visible, they still play an important part in computing.

 

[cliff]

What I am saying is that TSMC is a foundry, not a design house. The clock speed is probably on the design house (Intel vs AMD) side of the fence.