Can Post-layout simulation be done using partial tech-file?

[nitinthapliyal]

Is the technology file(i.e.LEF file) used during layout which contains layer,via,rules etc different from comp to comp(from ST to TI to Freescale)?
If yes, than does it contains any common information?
If yes, than what are those points?
Can i create this file manually(something which is specific be not mentioned and only common things described) and the cell libraries can automatically access the tech parameters as needed for them as these would be present in the lib cells also?

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[Daniel Payne]

The LEF file is an ASCII file with placement information about the Cells used in your IC design. It has the names of the Cells, pins and the metal layer for each pin. The DEF file has information on how the Cell pins are connected together.