Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/cadence-receives-tsmc-oip-ecosystem-forum-customers%E2%80%99-choice-award-for-n3-collaboration.13861/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Cadence Receives TSMC OIP Ecosystem Forum Customers’ Choice Award for N3 Collaboration

Daniel Nenni

Admin
Staff member

Cadence paper highlights how engineers can leverage the digital full flow and TSMC’s N3 process technology to advance hyperscale and mobile design​


SAN JOSE, Calif., 08 Mar 2021
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has received a TSMC Open Innovation Platform® (OIP) Ecosystem Forum Customers’ Choice award for a paper, “Optimized Digital Design, Implementation and Signoff on TSMC’s N3,” which was presented during the TSMC 2020 North America OIP Ecosystem Forum. Cadence’s Yufeng Luo, vice president, R&D in the Digital & Signoff Group, presented the paper, highlighting how engineers creating hyperscale and mobile designs can successfully benefit from the performance and efficiency of the TSMC N3 process technology and the Cadence® digital full flow.

The paper won the award based on the popular vote by conference attendees. Attendees had an opportunity to learn about new design techniques available with the N3-certified Cadence digital flow, which includes several feature enhancements—EUV layer support, route and via rules, cell placement, routing congestion avoidance, on-chip variation (OCV) accuracy and new signoff design rule checking (DRC) tools—to name a few.

“The Cadence digital full flow has been continuously optimized to support advanced N7, N6 and N5 production designs and now also supports TSMC’s latest N3 process technology,” said Cadence’s Luo. “This recognition further indicates our commitment to collaborating with TSMC to facilitate advanced-node design, and we look forward to seeing our mutual customers achieve success with our digital full flow and TSMC’s N3 process technology.”

“The Cadence paper presented at TSMC 2020 NA OIP Ecosystem Forum was an insightful overview as to how designers can achieve optimal power and performance using the latest Cadence and TSMC technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Enabling our customers to reach new milestones with mobile and hyperscale design development is the greatest reward that comes from our continued collaboration with Cadence.”


About Cadence​

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

For more information, please contact:​

Cadence Newsroom
408-944-7039
newsroom@cadence.com
 
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