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Industry Strength and EUV Demand Drive Expected Sales Growth of About 25 Percent in 2017 - Current Business Trends Likely to Continue into 2018
Seems like another solid quarter for ASML with EUV production capacity for 2017 (12 systems) and 2018 (20 systems + 4 upgrades) fully booked now.
It seems like Samsung ordered 6 additional EUV systems in Q2-17 (see slide 16): 8 additional NXE:3400B system orders received in Q2, with 6 orders from one customer for use in both Logic & DRAM
China also receives separate slides in their Q2-presentation about the growth of new fabs.
It has been reported (대한민국 IT포털의 중심! 이티뉴스) that Samsung already took one NXE3400 and is expecting a second one later this year, with 7 more next year. This was reported in the context of Samsung ramping up 6nm (7nm considered a little too late). If it is split between DRAM and foundry, then that's less for each.
This is an interesting slide. According to Samsung:
"I think our EUV process for 7nm can be called full EUV. When we introduce our process next year, we will have an advantage over them [tsmc=] in yield rate and price," Lee said.[/tsmc][tsmc=]
What exactly is "full EUV"? This is probably why TSMC refused to say how many EUV layers N7+ would have. To avoid a war of words with Samsung. TSMC did say:
Mark Lui: EUV is progressing rapidly, and we started the 7+ very early. And this EUV technology insertion in N7 is not only meant to do the cost reduction,the wafer cost reduction, but also to increase the density and increase the performance, transistor performance. So this technology is just -- notjust the cost reduction. It has the performance and density increases. As far as the EUV, I think we can reduce the cost by adopting the EUV on7-nanometer.
In regards to Samsung having better yield at 7nm, let me remind everyone that Samsung 10nm is a very poor yielding process. When Samsung announced that 10nm was in high volume production in Q4 2016 the yield was in single digits according to their largest customer. In fact, yield was so bad that Samsung had to charge for good die rather than wafers.
Given that TSMC 7nm leverages their 10nm fabs that are already in production (Apple) and TSMC N7+ EUV will be inserting EUV into an already high volume production process, I have a little doubt as to who will have the highest yielding 7nm EUV process. TSMC also added that EUV will give N7+ a performance and density advantage.
That is an interesting slide, surprised that ASML left out 1D single EUV exposure option. Going from 2D triple patterning to 1D with EUV (with or w/o SAQP) will be a difficult transition.
