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Architect- Analog Design (HBM PHY and Specialty I/O) - US/California or Italy/Pavia

Sheila

New member

Analog Design Engineer/Architect


eSilicon
has a world-class custom IP team with a successful track record of first-time silicon success and demonstrated ability to provide differentiated IP cores at leading-edge process nodes. We are seeking a seasoned, hands-on Analog Design Engineering Leader in either San Jose, CA or Pavia, Italy to join this team and define the architecture of eSilicon’s HBM PHY and specialty I/O products and oversee their implementation.

Responsibilities include:

  • Work with marketing and customers to understand market trends, industry standards, and the competitive environment for the HBM PHY and specialty I/O products.
  • Define the architecture for these products and work with the implementation team to refine the architecture, develop the execution plan and schedule, and deliver working silicon
  • Lead, review and approve the implementation of these products working across multiple engineering teams in multiple locations
  • Work with internal ASIC engineering teams and external customers to ensure their success in using the products
  • Mentor the implementation team in analog design techniques to continuously improve their capabilities

Background and Experience Requirements:

BSEE/MSEE plus 10-15 years of experience in analog design which includes:

  • Deep knowledge of a wide range of complex analog mixed signal design elements in leading-edge FinFET process nodes such as switching and linear regulators, charge pumps, PLLs, ADCs, DACs, load switches, bandgap bias, sequencers, LNA’s, RF TX/RX and precision analog blocks.
  • Knowledge of memory interface architectures such as DDR, LPDDR, GDDR, or HBM.
  • Advanced knowledge in EDA, tools, design flow and strong experience with IC design and simulation tools such as Spectre, SPICE, HSIM, Verilog-A, MATLAB, etc.
  • Advanced knowledge of semiconductor physics and new process technology limitations including an understanding of layout and proximity effects on circuit performance
  • Experience taking designs from the architecture phase through implementation and ultimately validation in silicon
  • Emphasis on high quality designs and customer deliverables, manufacturability and high product yield
  • Strong lab and silicon validation skills for the evaluation of product and test circuit performance.
  • Experience establishing and maintaining working relationships with key industry partners and suppliers.
  • A strong demonstrated commitment to teamwork and working with internal and external customers.
  • Strong communication skills, with the ability to convey complex technical concepts to others in verbal and written form.
  • Direct functional management of engineering team(s) or Project Leadership experience
  • Well respected by technical colleagues and enjoys mentoring, leading less experienced design engineers.

  • Must be eligible to work in location of hire (either US or Italy) without restriction(s)
  • Regular travel to Asia is required
  • Local candidates (San Jose, California, or Italy given preference (no relocation))
  • Only candidates who meet the requirements listed will be considered.

Please feel free to contact me directly if you meet the qualifications above.
 
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