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Per Dr J Class in Taiwan, M1 Ultra is using InFO-L, not CoWoS. Anybody know more about the UltraFusion specs: pJ/bit, bps/lane, beachfront density, etc?
Per Dr J Class in Taiwan, M1 Ultra is using InFO-L, not CoWoS. Anybody know more about the UltraFusion specs: pJ/bit, bps/lane, beachfront density, etc?
I just checked the die size for M1 Max at ~20 mm x 21.6mm according to AnandTech (or 19 mm x 22 mm according to TechInsights), so the two of these making up M1 Ultra cannot possibly fit into a single exposure field (26 mm x 33 mm). So the Ultra size must be defined by the CoWoS interposer. M1 Ultra should be considered a type of SiP (System-in-Package), not SoC. It's two chips packaged together.
Actually the Si interposer is quite small, much smaller than reticle. The Si interposer is embedded in the RDL. See around 7:30 minutes, the Si interposer (矽中介板) is the small green section in the middle.
Actually the Si interposer is quite small, much smaller than reticle. The Si interposer is embedded in the RDL. See around 7:30 minutes, the Si interposer (矽中介板) is the small green section in the middle.
Info-L has two parts: the Silicon interposer (green) is reticle-limited, but the RDL (substrate, red in Dr J's picture) is not limited to a reticle size. In fact the substrate (RDL) looks like it actually also contains the 8xDRAM chips.
The Info-L one-reticle size specification is a bit confusing:
For sure, M1 Ultra is larger than 1 reticle. Generally, we would expect the whole RDL to be so as well. So, not sure if the 1X reticle limitation above is for special chiplet cases only.
I think that's the case. I don't think exposure is required for RDLs. It looks like expensive variant of EMIB to me.
Intel EMIB : Uses silicon interposer(bridge-like) between substrates, TSV not supported
TSMC InFO-L : Uses LSI(A piece of silicon) in RDLs, TSV supported, LSI can be somehow active die
Info-L has two parts: the Silicon interposer (green) is reticle-limited, but the RDL (substrate, red in Dr J's picture) is not limited to a reticle size. In fact the substrate (RDL) looks like it actually also contains the 8xDRAM chips.
Question, MU worked with Generative Adversarial Networks to use AI's to do the actual programing, is their any possibility Apple could be headed in this direction using the two cores as adversarial networks?
They could in theory dice the wafer up into pairs of M1 die; if you look at the layout one reticle on the M1 Ultra appears to be rotated 180 degrees compared to the other, and there could be interconnect on the silicon between the two crossing what would be the (non-scribed) scribe channel. But this would definitely cause some interesting manufacturing problems since either the reticle would have to be rotated or dual reticles used, one for each way up.
Or they could butt two M1 Max dies up to each other on the silicon interposer, where the gap is too small to see on the photos (usually less than 100um). Which would also help yield, so this is a more likely option.
On March 8, Apple held their “Peek Performance” event, introducing the all-new Mac Studio and Studio Display, a new iPad Air, the new iPhone SE, and two new shades of green for the iPhone 13 and iPhone 13 Pro.
