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Achronix Ships 10 Millionth Speedcore eFPGA IP Core

Daniel Nenni

Staff member
Achronix has shipped over 10 million Speedcore eFPGA IP cores in customers' ASICs

This milestone represents proven industry acceptance of our industry-leading eFPGA IP technology. eFPGA IP from Achronix is being developed across a wide range of applications from 5G wireless, storage, networking and automotive driver assistance systems (ADAS). Check out our press release highlighting this significant industry milestone.

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Achronix in the News​

Achronix Semiconductor to List on Nasdaq as Publicly Traded Company

We are excited to announce that Achronix Semiconductor Corporation and ACE Convergence Acquisition Corp. (Nasdaq: ACEV), a special-purpose acquisition company (SPAC), have entered into a definitive agreement that will result in the combined entity continuing as a publicly traded company. As the only independent high-end FPGA and eFPGA IP company, Achronix will be well positioned to continue to capitalize on the nearly $10B data acceleration market. It is expected for the deal to close by mid-2021 and Achronix will then be traded under new ticker symbol ACHX.

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Achronix and Logic Fruit Introduce IP Solutions for Test and Measurement Applications

Achronix and Logic Fruit announced a partnership to develop optimized IP for test and measurement applications. These solutions will leverage the Speedster7t FPGA's high performance I/O which include 112 Gbps SerDes, PCIe Gen5 and GDDR6 interfaces. All of these interfaces are connected using Achronix's proprietary 2D NoC to provide >20Tbps of bandwidth.

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Achronix and Mobiveil Announce Partnership to Deliver High-Speed Controller IP and FPGA Engineering Services

Achronix and Mobiveil, a fast‐growing technology company specializing in development of silicon intellectual property (SIP), platforms and solutions for storage, networking, AI and enterprise markets, announced a partnership to offer Mobiveil’s soft IP portfolio to designers targeting Achronix devices. This partnership provides Achronix customers access to high performance controller IP and design services to accelerate their application development.

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Product News​

Download the latest version of the Achronix Design Tools

Make sure you have downloaded the latest version of ACE version 8.3.2. The latest version includes:
  • Up to 20% runtime improvement over ACE 8.3.1
  • Updates to the I/O designer toolkit
    • Raw SerDes bitstream support
    • GPIO, CLKIO, and PLL bitstream support
    • New Advanced PLL GUI that includes spread spectrum and PLL bypass paths
  • Additional BRAM FIFO support in ACE library and GUI generator
  • Support for routing reset signals automatically on clock network for AC7t1500
  • New option to create obfuscated timing reports, allows customers to share post place and route netlists without sharing design secrets
  • New report_clock_regions command to generate reports on all nets routed on the clock network (includes clocks and other high-fanout nets)
Learn more and request an ACE evaluation license
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Best Practices in Designing Rad-Hard SoCs with eFPGA IP Webinar

Designing high-performance SoCs for data acceleration applications that require high levels of security and radiation tolerance is a significant challenge for the defense industry. These applications require new SoC design techniques in order to deliver electronics that are protected from malicious threats, supply chain issues and radiation exposure. This webinar will provide a technical discussion on the challenges and best practices involved in designing high-performance eFPGA IP for integration into custom radiation tolerant SoCs.

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Accelerating to 112 Gbps PAM4: Real-World FPGA Implementation Webinar

Accelerating data channels to 112 Gbps PAM4 forces system designers to balance increasing throughput, scalability and density demands with concerns such as signal integrity, system architectures and time-to-market. In this webinar, technical experts from Achronix and Samtec discuss real-world tools and solutions that optimize the signal path both inside and outside the system design. Achronix and Samtec provide a real-world case study of implementing 112 Gbps PAM4 links using Achronix Speedster7t FPGAs and Samtec’s portfolio of high-performance interconnect solutions.

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Maximize Performance Using FPGAs with PCIe Gen5 Interfaces Webinar

In this webinar, you will learn how to maximize design performance using FPGAs with embedded PCIe Gen5 interfaces. You’ll see why, in addition to high-speed connectivity, you need the ability to process incoming high-bandwidth data to accelerate application performance. You'll learn how to maximize application bandwidth using FPGAs that include embedded PCIe Gen5 x16 interfaces capable of 512 GT/s, high-speed 2D network on chip (NoC) capable of delivering more than 20 Tbps of bandwidth, high-performance GDDR6 memory interfaces, optimized arithmetic units designed to support number formats needed for AI / ML workloads. We also highlight several application use cases for PCIe Gen5 enabled FPGAs along with important FPGA design considerations to ensure maximum efficiency and bandwidth.

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How Customers Will Benefit from Achronix Going Public

Read the latest blog post from Achronix that explains some of the benefits that our current and future customers will realize by Achronix going public. Learn how the capital raised will be used to accelerate our product development activities.
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Articles and Interviews​

Documentation Updates​

Migrating to Achronix FPGA Technology

Many users transitioning to Achronix FPGA technology will be familiar with existing FPGA solutions from other vendors. Although Achronix technology and tools are similar to existing FPGA technology and tools, there are some differences. Understanding these differences are needed to achieve the very best performance and quality of results (QoR).

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The AI Evolution Calls for Adaptable Inference Platforms

With AI and deep learning models growing at rates faster than Moore's Law, a new challenge has emerged to develop heterogenous hardware acceleration platforms that can keep up with this growth. This growth has lead to the adoption of FPGA technology that supports the number formats that are now commonly used in these models. Learn how Speedster7t FPGAs with their machine learning processors that natively support multiple different number formats can accelerate AI applications and support the latest AI and deep learning.

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FPGAs for Advanced Video Processing Solutions

While the performance of an ASIC is typically high enough for broadcast-quality video processing, it supports only the feature set conceived of at design time and is not field upgradable. A CPU is the most flexible; however, clock frequencies have plateaued, and the era of dramatic improvements in performance are over. FPGAs represent a good balance between performance and flexibility for this class of application.

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