The mask count from 10nm to 5nm was comparable according to TSMC (at IEDM 2019). The main point they made was they had expected many more masks at 5nm without EUV.
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That said, they do have special EUV mask handling in the fab (cleaning) due to lack of pellicles.
Thank you Fred. If not for EUV we would be using octuple patterning for 3nm?