Daniel Payne
Moderator
Call for Papers
The 29th International Workshop on Logic & Synthesis - IWLS 2020
July 18 - 19, 2020, Moscone Center, San Francisco, CA
(co-located with IEEE/ACM Design Automation Conference)
Website: http://www.iwls.org
Paper abstract submission: April 17, 2020
Full paper submission: April 24, 2020
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The International Workshop on Logic & Synthesis is the premier forum for research in synthesis, optimization, and verification of integrated circuits and systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.
Topics of interest include, but are not limited to hardware synthesis and optimization; software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.
===== Important Dates =====
Paper abstract submission: April 17, 2020
Full paper submission: April 24, 2020
Notification of acceptance: June 5, 2020
Final version due: July 3, 2020
===== Paper submission =====
Only complete papers with original and previously unpublished material are permitted. Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.
The submission system is available at http://www.iwls.org
===== Programming Contest =====
The IWLS 2020 edition will also have a programming contest. More information will be available at http://www.iwls.org.
===== Contact =====
General Chair: Pierre-Emmanuel Gaillardon, University of Utah, USA
Program Chairs: Luca Amaru / Heinz Riener, Synopsys, USA / EPFL, Switzerland
Programming Contest Chair: Gai Liu, Xilinx Inc, USA
Special Session Chair: Tsung-Yi Ho, NTHU, Taiwan
Finance Chair: Cunxi Yu, University of Utah, USA
Proceedings Chair: Zhufei Chu, Ningbo University, China
Publicity Chair: Tsung-Wei Huang, University of Utah, USA
Local Chair: Vinicius Callegaro, Mentor, a Siemens Business, USA
===== Program Committee =====
Luca Amaru Synopsys, USA
Anna Bernasconi University of Pisa, Italy
Vinicius Callegaro Mentor, a Siemens business, USA
Kai-Hui Chang Avery Design Systems, USA
Mihir Choudhury IBM T. J. Watson, USA
Zhufei Chu Ningbo University, China
Sabya Das Synopsys, USA
Rolf Drechsler University of Bremen, Germany
Elena Dubrova KTH, Sweden
Stephen Edwards Columbia University, USA
Petr Fiser CTU, Czech Republic
Masahiro Fujita University of Tokyo, Japan
Pierre-Emmanuel Gaillardon University of Utah, USA
Tsung-Yi Ho NTHU, Taiwan
Tsung-Wei Huang University of Utah, USA
Paolo Ienne EPFL, Switzerland
Iris Jiang National Taiwan University, Taiwan
Jie-Hong Roland Jiang National Taiwan University, Taiwan
Victor Kravets IBM T. J. Watson, USA
Gai Liu Xilinx Inc, USA
Felipe Marranghello Synopsys, USA
Mayler Martins Mentor, a Siemens business, USA
Jody Matos Silvaco, USA
Alan Mishchenko UC Berkeley, USA
Augusto Neutzling Cadence, UK
Vinicius Possani Synopsys, USA
Madhura Purnaprajna Amrita University, India
Weikang Qian Shanghai Jiao Tong U., China
Andre Inacio Reis UFRGS, Brazil
Heinz Riener EPFL, Switzerland
Tsutomu Sasao Meiji University, Japan
Mathias Soeken Microsoft, USA
Dirk Stroobandt Ghent University, Belgium
Tiziano Villa Universita' di Verona, Italy
Robert Wille Johannes Kepler U., Austria
Cunxi Yu University of Utah, USA
Zhiru Zhang Cornell University, USA