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Staf_Verhaegen
Guest
ASML only has a monopoly because no other company seem to be able to compete on a technical level with them. As I said before, blaim the competition not ASML.
2016 Semi Capex & Seasonality trends- 10nm rollout- Multi-Patterning vs. EUV
- Thread starter Robert Maire
- Start date
ASML only has a monopoly because no other company seem to be able to compete on a technical level with them. As I said before, blaim the competition not ASML.
Brianhayes
New member
Thanks for your comments. I was not aware that ASML had a virtual monopoly already but it does rather suggest that it has little incentive to drive EUV on. You refer to the article in mid 2014 but I remember the announcement of Intel's investment in July 2012 and the acquisition of Cymer in October both of which emphasised the importance given to EUV. Fast forward to TSMC's transcript two days ago and this is what Mark Liu had to say.
Yes, we plan to use EUV on our 5-nanometer. And we have already three EUV tools on the floor and the fourth is coming. So all these are using actively for the development. So until 2020, when N5 is currently planned into production, yes, it will be adopted.
But just to remind you that in -- if you think about CapEx, don't think about everything we're going to change to EUV. There are 80 layers and only a 10 -- there are about 50/60 if you discount multiple patterning. Only the 10 of them roughly will use EUV. So a lot of tools still be able to common tools.
At one stage TSMC was "planning" to introduce EUV at 16nm; now they are discussing 2020. I don't think somehow that the issue is lack of pellicles. I do suspect, however, lack of motivation. There may be no one complaining but there are plenty of articles saying that development costs below 28nm have risen sharply with a corresponding reduction in IC starts. The point of EUV of course is to reduce costs from multi patterning, aka multi use of ASML tools.
I do do not so much criticise ASML for being a monopoly as Intel for allowing it to happen and, with respect to EUV, paying for it. It beats me how they ponied up €3.1bn without any say in where the money was to go or any real assurances that EUV would be delivered. As I said ASML has no incentive even now to produce it. In fact it might not even be considered businesslike for it to do so.
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I suspect Intel, Samsung and TSMC are attempting to force ASML to accept a low price for EUV equipment. Octo-patterning is a straw man for negotiating purpose. On the other hand, ASML can threaten Intel, Samsung and TSMC existence. My opinion, that ensures fair treatment for ASML. Good for them.
Now for some juicy speculation. EUV is the Ferrari of lithography, and not everyone can afford such nice wheels. What if Intel has mastered EUV and doesn't want to share? Fund ASML purchase of Cymer, and encourage ASML to price EUV out of Samsung and TSMC budget. Result: Intel dominance at 10nm and below.
Now for some juicy speculation. EUV is the Ferrari of lithography, and not everyone can afford such nice wheels. What if Intel has mastered EUV and doesn't want to share? Fund ASML purchase of Cymer, and encourage ASML to price EUV out of Samsung and TSMC budget. Result: Intel dominance at 10nm and below.
hist78
Well-known member
Yes, Intel can do that. But the following circumstance must occur:
1. Intel must convince regulators that Intel is not violating antitrust regulations. With so many leaks every now and then, such as Edward Snowden, Wikileak, and Panama Papers, I don't think Intel will even dare to discuss this strategy internally, never mind to implement it.
2. ASML must make EUV almost like the ONLY solution for everything after certain node, such as 5nm process. Otherwise setting an extreme price to push out TSMC or Samsung is a suicide strategy for ASML itself.
3. If an ASML executives helps Intel to push out TSMC or Samsung by setting extreme high priced EUV equipment, he or she will be push out by shareholders too. The ASML's board has to consider its legal and reputation issues if they allow this to happen.
4. Intel has to have many unique and superior technology breakthrough directly or indirectly related to EUV that no any other company can achieve or even imagine. So ASML is limited to be a simple tool or machine vendor who knows nothing else. In this case, Intel doesn't need ASML to begin with. Considering Intel's bank accounts, Intel can easily build an EUV division internally to replace ASML. Right? Especially after ASML kicks TSMC and Samsung out, Intel will be the only leading edge fab customer of ASML. This can happen, but IMHO it's very unlikely.
5. ASML must be lazzy enough and want to deal only one customer, Intel.
6. ASML doesn't like to make more money. Any amount of money they make from Intel is good enough to ASML executives and shareholders.
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Brianhayes
New member
Great idea! But somehow I think that old fox Chang has the measure of Krzanich.
I think you have too high an opinion of EUV. A lot of things still don't work.
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Intel still would need a second source supplier even with EUV technology.
Brianhayes
New member
I would add a speculation of my own, which is part of an explanation I have been looking for why Intel stumbled so badly at 14nm and appear to have lost their much vaunted process lead.
In 2012 Morris Chang said publicly that he believed that 16nm required EUV. He is the one individual in semiconductors that I would never consider betting against. When he made that comment TSMC was working on double patterning at 20nm so I now surmise they were finding it difficult.
In the event Intel produced Finfets at 22nm and at Computex in June 2013 unveiled the Atom architecture. The spin machine went into overdrive declaring victory in mobile and my broker told me to sell ARM (I did not). The victory celebrations lasted until Apple produced the A7 in September. Part of all this was the rubbishing of TSMC's 20nm process and specifically its DPT. It was too expensive and Finfets of course were so much better. The A7 of course when it arrived beat the Atom products and by a mile.
I can now see that TSMC mastered double patterning many months - maybe years - before Intel and moved without a hitch and in record time to Finfets at 16nm. Commenting on the 14nm process Morris Chang said, "they will find it difficult." It was not obvious to me at the time whether he was referring to Intel or Samsung.
Now the old fox has sold his shares in ASML cashing in a tidy profit. Maybe he shares (and shared in 2012) the doubts on EUV that many subscribers to Semiwiki have. Maybe Intel decided to go all in on EUV in 2012/2013 and found out too late that they had to learn DPT. Maybe, in other words, they actually believed their own spin.
This is is all speculation but as Intel tells its shareholders nothing speculation is all there is. The defeat at 14nm was a heavy one.
Will EUV be the only solution below 5nm? For that matter is octo-patterning real? Is there anything else?
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Staf_Verhaegen
Guest
Are you serious about this comment ? Litho is the most complex processing step in the micro-electronics processing and likely the most complex volume produced machine in manufacturing (discounting the LHC etc.).
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hist78
Well-known member
Of course, I'm joking!
As it stands today, I have much more faith in device and lithography people than ASML. From what I am told quad patterning at 10nm is going much better than projected and 7nm (also quad patterning) will be ready to go in 2018.
For 5nm, the negative-capacitance transistor (NC-FET), Chenming Hu's latest effort, is seriously being considered by the foundries. If so, will EUV still play a role? Or will quad patterning be sufficient?
For 5nm, the negative-capacitance transistor (NC-FET), Chenming Hu's latest effort, is seriously being considered by the foundries. If so, will EUV still play a role? Or will quad patterning be sufficient?
Brianhayes
New member
It looks as if TSMC is on top of this. On NC-FETs the papers from SNUG suggest that Intel and TSMC may be cooperating. Is the world about to change? The material I have read does not suggest 2020 as a likely ETA.
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Staf_Verhaegen
Guest
Don't forget that it is also ASML who helps enable quad patterning etc. The specs of their immersion machines take into account these use cases.
I think the question is if EUV can ever be made economically viable and that only future can tell. If so, it will replace several immersion+processing steps with a smaller number of EUV+processing steps and/or relieve the restricted design rules.
What does surprise me, is that EUV seems to have become a matter of believing or non-believing. Personally I don't mind if my chips are produced under water or in vacuum, as long as my Chinese cell phone is cheap enough and maybe in the future can become intelligent.
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The new thing for NC-FETs is ferroelectrics. Handling them is non-trivial, just ask the FeRAM or FRAM guys.
Brianhayes
New member
This is absolutely the right question but for the future to tell us the answer, someone has to commit, maybe, two or three $billion to find out if it works. I do not see the candidates. Intel has burn't its fingers and TSMC is unlikely to step in without a customer that says it must happen (and put up the risk money). There is only one candidate for that role and I would not suggest it is probable, even if you presuppose that EUV is the ONLY way to proceed with Moore's Law.
Scotten Jones will be attending the imec Technology Forum in Brussels next month. imec is on the leading edge of process development research so look for some interesting blogs from Scott:
Imec ITF - Program
ITF Brussels is the flagship of the worldwide series of Imec Technology Forums. Each year, we gather experts and visionaries in a two-day event to discuss the future in technology and bringing tech-innovation to market. Two days packed with exclusive keynotes, insightful presentations and networking opportunities. Two days at an unique conference venue in the heart of Brussels.
This year’s theme is: "Daring to take a different view - Nanotechnology in the hot seat"
Innovation doesn’t always come with a single spark of insight. It’s often the result of endless questions, discussions, challenges, and being daring enough to toss out solutions that may seem smart, but just aren’t the right answer.
At ITF2016, we will look at nanotechnology from different angles, question its future course, identify its use in new applications, and offer different paths for powering the future through the power of nanotechnology.
Innovation is your and our work. Join us at ITF2016 as we put speakers and ideas in the hot seat to find solutions together.
Imec ITF - Program
ITF Brussels is the flagship of the worldwide series of Imec Technology Forums. Each year, we gather experts and visionaries in a two-day event to discuss the future in technology and bringing tech-innovation to market. Two days packed with exclusive keynotes, insightful presentations and networking opportunities. Two days at an unique conference venue in the heart of Brussels.
This year’s theme is: "Daring to take a different view - Nanotechnology in the hot seat"
Innovation doesn’t always come with a single spark of insight. It’s often the result of endless questions, discussions, challenges, and being daring enough to toss out solutions that may seem smart, but just aren’t the right answer.
At ITF2016, we will look at nanotechnology from different angles, question its future course, identify its use in new applications, and offer different paths for powering the future through the power of nanotechnology.
Innovation is your and our work. Join us at ITF2016 as we put speakers and ideas in the hot seat to find solutions together.
ASML's conference call transcript:
ASML Holding's (ASML) CEO Peter Wennink on Q1 2 16 Results - Earnings Call Transcript | Seeking Alpha
Orders fell 30%?
EUV was not discussed in detail and based on what I know there is good reason for that. 10 layers of EUV was mentioned at 7nm? That must be Intel because it is not TSMC. Intel 7nm could very well be pushed out to > 2020 which is the earliest EUV will hit HVM, just my opinion of course.
ASML Holding's (ASML) CEO Peter Wennink on Q1 2 16 Results - Earnings Call Transcript | Seeking Alpha
Orders fell 30%?
EUV was not discussed in detail and based on what I know there is good reason for that. 10 layers of EUV was mentioned at 7nm? That must be Intel because it is not TSMC. Intel 7nm could very well be pushed out to > 2020 which is the earliest EUV will hit HVM, just my opinion of course.
Interesting, on the last page, ASML was asked about the 15-tool order from Intel. Actually, it was a purchase agreement, to submit those orders according to some "pre-determined pattern." So, no orders yet?
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Staf_Verhaegen
Guest
From the other side Intel, TSMC, etc. keep the EUV research going. EUV is a (big) research topic in imec's program and this is paid by the partners. They include Intel, TSMC etc. If these partners decide it is not worthwhile anymore EUV will die.