Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/roger-espasa-participated-at-the-spring-2022-risc-v-week-with-the-talk-atrevido-semidynamics-out-of-order-risc-v-core.17818/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Roger Espasa participated at the Spring 2022 RISC-V week with the talk "Atrevido: Semidynamics Out-of-Order RISC-V Core"

AmandaK

Administrator
Staff member
April 12, 2022

In this talk Roger Espasa described Atrevido, Semidynamic's out-of-order RISC-V Application core supporting the RISC-V vector extension. He covered the pipeline basics, the interplay between the vector specification and out-of-order execution and he discussed the Gazzillion(TM) misses feature, specifically tailored to support HPC vector programs.

Spring 2022 RISC-V Week's agenda

Link to Press Release
 
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