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Intel 18A tapeout without High-NA EUV

Fred Chen

Moderator
https://www.spiedigitallibrary.org/...ges-and-program/10.1117/12.2600951.full?SSO=1 "Buildings, cleanrooms and equipment are being constructed, mirror production is ramping up, many tests are carried out to ensure a smooth implementation." (Sept 27 2021)

https://www.spiedigitallibrary.org/...duction-in-2025/10.1117/12.2622177.full?SSO=1 (April 25, 2002) Target availability in 2023 for OPC development etc.

https://wccftech.com/intel-updates-...-rapids-sierra-forest-2023-20a-18a-taped-out/ "On Intel 20A and 18A, the first nodes to benefit from RibbonFET and PowerVia our first internal test chips, and those of a major potential foundry customer have taped out with silicon running in the fab." (Intel Q3 2022 earnings call)
 
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Man how has intel tapped out 18A. I thought they needed the new High NA EUV's for 18A. I guess I must be thinking about 16A.
Their roadmap says it is their goal to merge it with 18A, but that it isn’t required (Think n7. It didn’t need EUV but when it was ready they inserted limited amounts of it into the process flow). It seems intel is not making the same mistake as they made with 10nm (designing in a non flexible manner) or what seems to have been one of 7nm’s issues (being multiple rearchitectings as they went back and forth on EUV readiness).
 
It's projected to be ~18 nm minimum metal pitch: https://www.semi.org/sites/semi.org/files/2022-03/SEMI EMG Presentation for 20220323 final for presentation.pdf

That would most likely mean 4-mask SALELE on the track layer. 25 nm pitch via patterning would also be quadruple patterning.
In the presentation you linked, TSMC would have to deal with the same issues. I would have to assume that intel's experience with 10/7/4/3 would allow them to navigate this issue slightly easier than other foundries that haven't used SAQP for their BEOL. Also worth noting is that these projections are already too big for actual i4 metal pitches (28 vs 30nm).

When you say 25nm would be quad patterning do you mean DUV or do you mean EUV quad?
 
It's projected to be ~18 nm minimum metal pitch: https://www.semi.org/sites/semi.org/files/2022-03/SEMI EMG Presentation for 20220323 final for presentation.pdf

That would most likely mean 4-mask SALELE on the track layer. 25 nm pitch via patterning would also be quadruple patterning.
I can't believe I forgot about backside power rails. In theory doesn't backside power delivery allow intel to have larger metal pitches than what would be required from everyone else's offerings? Or would first generation powervia not really impact M0 pitches?
 
In the presentation you linked, TSMC would have to deal with the same issues. I would have to assume that intel's experience with 10/7/4/3 would allow them to navigate this issue slightly easier than other foundries that haven't used SAQP for their BEOL. Also worth noting is that these projections are already too big for actual i4 metal pitches (28 vs 30nm).

When you say 25nm would be quad patterning do you mean DUV or do you mean EUV quad?
EUV quad. The reason for this is the minimum via center-to-center is ~38 nm.

Reference: W. Gao et al., Proc. SPIE 11323, 113231L (2020).


Via_Triple_Patterning_for_EUV.png

 
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I can't believe I forgot about backside power rails. In theory doesn't backside power delivery allow intel to have larger metal pitches than what would be required from everyone else's offerings? Or would first generation powervia not really impact M0 pitches?
I think they would keep the minimum track pitch, but by moving the power/ground rails underneath, their normally wider footprint would be saved.
 
EUV quad. The reason for this is the minimum via center-to-center is ~38 nm.

Reference: W. Gao et al., Proc. SPIE 11323, 113231L (2020).


Via_Triple_Patterning_for_EUV.png

Let me see if I understand that litho presentation you linked. At "3nm" metal pitches can't really go below 42nm at the moment without having via placement error screwing you over. You can go to double and triple patterning (depending on design rules) to fix this, or you can reduce intensity (hurting output) while also having yet invented resits and masks. The final solution is self aligning the vias which isn't economical at this point in time.

For intel specifically, if they were willing to sacrifice some of the potential std cell density uplift on 20/18A they could widen track width/by extension metal pitch to reduce the amount of multi patterning that is necessary. This also brings up the question, is it known weather 20A will bring a significant improvement to density since intel is moving to modular development?
 
After all this time, including time spent with TSMC over 3nm, Intel 18A will not have lower minimum metal pitch than Intel 4.

 
After all this time, including time spent with TSMC over 3nm, Intel 18A will not have lower minimum metal pitch than Intel 4.

Considering one of the early Pat era press briefs said intel was developing nodes in a modular manner and that they were derisking powervia with a intel 3 test node, I was curious if this would be the case.

Is it still possible to shrink std cells by reducing track number or cpp, or has intel 4 shrunk it by about as much as is physically possible? We know that 3 and 18A are supposed to be slightly shrunk, So I’m curious what is actually being shrunk.

Edit: Some additional thoughts. Interesting that the company that once pushed density as hard as possible (to the point of using quad patterning at 10nm) doesn’t want to use SALELE. Also given the bidirectional nature, and direct print EUV, I can see customers loving this node. The cost/speed per the performance/leakage uplift should be nice. Additionally unlike 14/10nm 18A should be easy (for its time) to design. The caveat for this being that there will probably be many rules so people don’t nuke their performance with bad metal routing.
 
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Considering one of the early Pat era press briefs said intel was developing nodes in a modular manner and that they were derisking powervia with a intel 3 test node, I was curious if this would be the case.

Is it still possible to shrink std cells by reducing track number or cpp, or has intel 4 shrunk it by about as much as is physically possible? We know that 3 and 18A are supposed to be slightly shrunk, So I’m curious what is actually being shrunk.

Edit: Some additional thoughts. Interesting that the company that once pushed density as hard as possible (to the point of using quad patterning at 10nm) doesn’t want to use SALELE. Also given the bidirectional nature, and direct print EUV, I can see customers loving this node. The cost/speed per the performance/leakage uplift should be nice. Additionally unlike 14/10nm 18A should be easy (for its time) to design. The caveat for this being that there will probably be many rules so people don’t nuke their performance with bad metal routing.
CPP cannot be aggressive shrink, perhaps track number. 30-36 nm pitch direct print is still unidirectional lines and cuts. Perhaps they mean to allow both x and y lines, each unidirectional.
 
30-36 nm pitch direct print is still unidirectional lines and cuts. Perhaps they mean to allow both x and y lines, each unidirectional.
As in you can have only straight lines but now you can choose which direction those lines move in?
 
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