EUV stochastic defects plague Samsung's yield, even with double patterning

[Fred Chen]

Advanced interconnect challenges beyond 5nm and possible solutions

As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance, yield, and cost. Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the...

ieeexplore.ieee.org

Abstract:
As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance, yield, and cost. Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the resistivity of damascene Cu lines, grain size and interface engineering are being investigated, as well as a new liner that can enable more aggressive thickness scaling. To improve capacitance, k-value reduction of dielectric films by damage recovery during process integration is being studied. Yield loss is mainly attributed to micro bridge, also known as stochastic printing failures of EUV lithography, or scaling induced Cu void or bridge defects. New photoresists or etch process recipes are being explored in order to address the micro bridge. Cu-fill friendly damascene profile is being introduced to suppress Cu void defects. Since rising BEOL cost is a critical challenge, single EUV patterning to replace double patterning is being actively investigated. In parallel to the conventional scaling, disruptive interconnect architectural changes such as backside power distribution network, and innovative materials such as alternative conductors, and 2D barriers / liners need to be considered.

 

[Paul2]

Advanced interconnect challenges beyond 5nm and possible solutions

As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance, yield, and cost. Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the...

ieeexplore.ieee.org

Abstract:
As the on-chip interconnect scales down to below 30nm pitch, it faces challenges in all aspects of performance, yield, and cost. Performance degradation caused by electron scattering in narrow Cu damascene lines, combined with slow barrier/liner scaling is a big concern. In order to reduce the resistivity of damascene Cu lines, grain size and interface engineering are being investigated, as well as a new liner that can enable more aggressive thickness scaling. To improve capacitance, k-value reduction of dielectric films by damage recovery during process integration is being studied. Yield loss is mainly attributed to micro bridge, also known as stochastic printing failures of EUV lithography, or scaling induced Cu void or bridge defects. New photoresists or etch process recipes are being explored in order to address the micro bridge. Cu-fill friendly damascene profile is being introduced to suppress Cu void defects. Since rising BEOL cost is a critical challenge, single EUV patterning to replace double patterning is being actively investigated. In parallel to the conventional scaling, disruptive interconnect architectural changes such as backside power distribution network, and innovative materials such as alternative conductors, and 2D barriers / liners need to be considered.

Have you heard any news on monocrystalline interconnect developments lately?

 

[Fred Chen]

Have you heard any news on monocrystalline interconnect developments lately?

Nothing particularly. Presumably the grain size is large enough for it to be not significant, compared to the wire boundary itself.

 

[Paul2]

Nothing particularly. Presumably the grain size is large enough for it to be not significant, compared to the wire boundary itself.

What's significant is the grain orientation, or at least this is what I was reading 10 years ago. The idea was to get conductor lattice to be coplanar to the wafer

 

[semiman]

I think this is one of the reasons why DTCO has become so important. Shorter wavelength and smaller patterns always result in stochastic failures. Foundries can try to mitigate failures by using many techniques but it's always best if risky patterns are avoided by fabless themselves.