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TSMC Details The Benefits of Its N3 Node

P

prime007

Active member
This EE Times article ties together various sources of information regarding TSMC's N3 Node.
Quick summary: Speed improvement is at the low-end of TSMC's projections (11%), Logic density misses TSMC's projection (1.6x vs projected 1.7x) and power draw improvement is 27% going from N5 to N3
https://www.eetimes.com/1383768-2/
 
Note that by using the HPC DTCO option to trade off power/speed against area, speed increase is +19% and power saving is -39%, and in most cases nowadays these are the main reason to move down a process node rather than gate density.
 
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