Company to present differentiating, low power analog foundation IP and SERDES technology at Samsung Foundry SAFE Forum 2020
Highlights
¤ Portfolio of clocking, sensor, I/O and SERDES IP available on 32LP, 28LPP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE technologies to be presented at the Samsung Foundry SAFE Forum 2020 on October 28
¤ The challenges and requirements of AI chip design as well as application of SERDES technology in consumer and enterprise markets will be discussed, with a focus on the clocking, sensor, I/O and SERDES IP offered by Analog Bits
San Jose, California, October 28, 2020 – Analog Bits announced a comprehensive and differentiating foundation analog IP portfolio today on multiple Samsung Foundry technologies, including 32LP, 28LPP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE. The offering includes:
¤ Low power PLL
¤ PCIe reference clock
¤ Chip-to-chip I/O
¤ Clock TX/RX
¤ OSC pads
¤ PVT sensor
¤ Power supply glitch detectors
¤ High lane count, low power, multi-protocol SERDES optimized for PCIe protoco
Alan Rogers, president and CTO at Analog Bits, presented “PCIe SERDES - Gen4/5 Enterprise Class SERDES and Lowest Power Gen3/4 Automotive and Consumer SERDES in Samsung 28nm to 7nm Processes”. The presentation covered:
PCI Express SERDES Markets Needs – Consumer and Enterprise
Analog Bits SERDES Capabilities and Application Use – Low Power Full-Rate Architecture for Consumer Markets – High Performance Half-Rate Architecture for Enterprise Market
Silicon Results of PCIe Gen5
Collaboration and IP Availability at Samsung
Mahesh Tirupattur, executive vice president at Analog Bits, presented “Differentiated Low Power Analog Foundation IP – A Key Differentiator of AI SoCs” as well. The presentation covered:
Example of an AI Chip
Challenges and Requirement Needs of AI Chips
Capabilities Needed from Analog Foundation IPs – Clocking – Sensors – IOs – Analog Bits Analog Foundation IP offering in FinFET
Partnership with Samsung
“Samsung is proud to be working with Analog Bits for ten years,” said Jongshin Shin, Vice President of IP Development Team at Samsung Electronics. “Their quality and reputation for collaborative business practices have helped Samsung Foundry’s customers to succeed in the marketplace.” “Samsung is a long-term, trusted partner for Analog Bits,” said Alan Rogers, president and CTO of Analog Bits. “Mahesh and I look forward to presenting the details of our differentiating IP portfolio for their processes at SAFE Forum 2020.” Details of the Samsung SAFE Forum 2020 can be found here.
Highlights
¤ Portfolio of clocking, sensor, I/O and SERDES IP available on 32LP, 28LPP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE technologies to be presented at the Samsung Foundry SAFE Forum 2020 on October 28
¤ The challenges and requirements of AI chip design as well as application of SERDES technology in consumer and enterprise markets will be discussed, with a focus on the clocking, sensor, I/O and SERDES IP offered by Analog Bits
San Jose, California, October 28, 2020 – Analog Bits announced a comprehensive and differentiating foundation analog IP portfolio today on multiple Samsung Foundry technologies, including 32LP, 28LPP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE. The offering includes:
¤ Low power PLL
¤ PCIe reference clock
¤ Chip-to-chip I/O
¤ Clock TX/RX
¤ OSC pads
¤ PVT sensor
¤ Power supply glitch detectors
¤ High lane count, low power, multi-protocol SERDES optimized for PCIe protoco
Alan Rogers, president and CTO at Analog Bits, presented “PCIe SERDES - Gen4/5 Enterprise Class SERDES and Lowest Power Gen3/4 Automotive and Consumer SERDES in Samsung 28nm to 7nm Processes”. The presentation covered:
PCI Express SERDES Markets Needs – Consumer and Enterprise
Analog Bits SERDES Capabilities and Application Use – Low Power Full-Rate Architecture for Consumer Markets – High Performance Half-Rate Architecture for Enterprise Market
Silicon Results of PCIe Gen5
Collaboration and IP Availability at Samsung
Mahesh Tirupattur, executive vice president at Analog Bits, presented “Differentiated Low Power Analog Foundation IP – A Key Differentiator of AI SoCs” as well. The presentation covered:
Example of an AI Chip
Challenges and Requirement Needs of AI Chips
Capabilities Needed from Analog Foundation IPs – Clocking – Sensors – IOs – Analog Bits Analog Foundation IP offering in FinFET
Partnership with Samsung
“Samsung is proud to be working with Analog Bits for ten years,” said Jongshin Shin, Vice President of IP Development Team at Samsung Electronics. “Their quality and reputation for collaborative business practices have helped Samsung Foundry’s customers to succeed in the marketplace.” “Samsung is a long-term, trusted partner for Analog Bits,” said Alan Rogers, president and CTO of Analog Bits. “Mahesh and I look forward to presenting the details of our differentiating IP portfolio for their processes at SAFE Forum 2020.” Details of the Samsung SAFE Forum 2020 can be found here.