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A plot of accumulated immersion and EUV tools from Q1 2018 to Q2 2020 (from ASML's quarterly financial presentations) shows about 4x the accumulation rate for immersion compared to EUV. Assuming the WPD for immersion to be double (at least) compared to EUV, there is a difference in total wafer output rate of at least 8x. TSMC still has lots of immersion layers.
I roughly estimated EUV wafer usage from the graph. 7 million wafers over five quarters (150 days) over an estimated average of 45 tools, gives about 1000 wafers/day, per tool, which seems the right level of magnitude.