Daniel Payne
Moderator
Modeling of Systems and Parameter Extraction Working Group
Summary of the 11th International MOS-AK Workshop
Silvaco Inc. Headquarters, Silicon Valley, December 5, 2018
The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its 11th MOS-AK Workshop at the Silvaco Inc. headquarters in Santa Clara, Calif. on December 5, 2018. The event was co-located with the 2018 IEEE International Electron Devices (IEDM) and the Q4 Compact Modeling Coalition (CMC) meetings. The workshop receives technical program co-sponsorship from the IEEE Santa Clara Valley-San Francisco Chapter of the Electron Devices Society, Europractice, IJHSES as well as NEEDS of nanoHUB.org.
Bogdan Tudor, Silvaco Inc. and Wladek Grabinski, MOS-AK, welcomed more than 30 international academic researchers and modeling engineers. The nine technical compact modeling presentations covered nanoscale technologies, semiconductor devices modeling and advanced IC design.
The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. For more information about each of the presentations, including full abstracts, go online to MOS-AK Workshop Silicon Valley 2018.
The nine topics presented were the following:
There were also presentations of Late News with the following topics:
View attachment 22795
Photo: Some of the participants of the 11th MOS-AK Workshop at Silvaco Inc. headquarters in Silicon Valley.
The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in India, China, Europe, USA and, for the very first time, in Latin America, throughout the coming year, including:
About Silvaco:
Silvaco, Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.
About Europractice IC Service:
The EUROPRACTICE IC Service brings ASIC design and manufacturing capability within the technical and financial reach of any company that wishes to use ASICs. The EUROPRACTICE IC Service, offered by IMEC and Fraunhofer, offers low-cost ASIC prototyping and ASIC small volume production ramp-up to high volume production through Multi Project Wafer - MPW - and dedicated wafer runs.
About MOS-AK Association:
MOS-AK is an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for compact/SPICE model development, validation/implementation and distribution. For more information please visit mos-ak.org.
Summary of the 11th International MOS-AK Workshop
Silvaco Inc. Headquarters, Silicon Valley, December 5, 2018
The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its 11th MOS-AK Workshop at the Silvaco Inc. headquarters in Santa Clara, Calif. on December 5, 2018. The event was co-located with the 2018 IEEE International Electron Devices (IEDM) and the Q4 Compact Modeling Coalition (CMC) meetings. The workshop receives technical program co-sponsorship from the IEEE Santa Clara Valley-San Francisco Chapter of the Electron Devices Society, Europractice, IJHSES as well as NEEDS of nanoHUB.org.
Bogdan Tudor, Silvaco Inc. and Wladek Grabinski, MOS-AK, welcomed more than 30 international academic researchers and modeling engineers. The nine technical compact modeling presentations covered nanoscale technologies, semiconductor devices modeling and advanced IC design.
The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. For more information about each of the presentations, including full abstracts, go online to MOS-AK Workshop Silicon Valley 2018.
The nine topics presented were the following:
- Silvaco GaN HEMT Compact Modeling Perspective, Bogdan Tudor, Colin Shaw and Sungwon Kong, Silvaco, Inc.
- GaN HEMT Devices and Modeling for Operational Electronics at Harsh Environments, Saleh Kargarrazi, XLab, Stanford University
- Impact of Basal Plane Dislocations and Ruggedness of 10 kV 4H-SiC Transistors, Victor Veliadis, PowerAmerica, North Carolina State University
- Direct measurement of white noise in MOSFETs, Kenji Ohmori, Device Lab Inc.
- NEREID Technology Roadmap, Enrico Sangiorgi, NEREID, University of Bologna
- A Physics-Based Compact Model of RRAM for Emerging Applications, Paolo Pavan, University of Modena and Reggio Emilia
- From Physics to Power, Performance, and Parasitics, Oskar Baumgartner, Global TCAD Solutions GmbH
- MOS-AK FOSS Compact Modeling Perspective, Wladek Grabinski, IEEE EDS DL, MOS-AK
- Compact Model of Single TeraFET Spectrometer, Michael Shur, Rensselaer Polytechnic Institute
There were also presentations of Late News with the following topics:
- CMC Developer Model Software Licenses, Peter Lee, Micron
- Xyce Parallel Electronic Simulator (Ver. 6.10), Jason Verley, Sandia National Laboratories
- Call for Papers for ESSDERC/ESSCIRC 2019 in Krakow, Wladek Grabinski, MOS-AK
View attachment 22795
Photo: Some of the participants of the 11th MOS-AK Workshop at Silvaco Inc. headquarters in Silicon Valley.
The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in India, China, Europe, USA and, for the very first time, in Latin America, throughout the coming year, including:
- FOSDEM CAD/EDA DevRoom Feb. 2-3, 2019, ULB Solbosch
- 1st MOS-AK at LAEDC Feb. 25-28, 2019, Armenia, Columbia
- 2nd MOS-AK India Conference Feb. 25-27, 2019, IIT Hyderabad
- 4th Sino MOS-AK Workshop Jun. 20-23, 2019, UECST Chengdu
- MIXDES Special CM Session June 27-29, 2019, Rzeszow
- ESSDERC/ESSCIRC Sept. 23-26, 2019, AHG Krakow
About Silvaco:
Silvaco, Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.
About Europractice IC Service:
The EUROPRACTICE IC Service brings ASIC design and manufacturing capability within the technical and financial reach of any company that wishes to use ASICs. The EUROPRACTICE IC Service, offered by IMEC and Fraunhofer, offers low-cost ASIC prototyping and ASIC small volume production ramp-up to high volume production through Multi Project Wafer - MPW - and dedicated wafer runs.
About MOS-AK Association:
MOS-AK is an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for compact/SPICE model development, validation/implementation and distribution. For more information please visit mos-ak.org.