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Search results

  1. F

    EUV mask absorber issue

    At this year's SPIE, there are indications current EUV masks have problems with the Ta-based absorbers, leading to image fading. Image fading has been covered in two papers...
  2. F

    Samsung chip profitability expected to be driven by higher memory prices, HBM

    https://www.reuters.com/technology/samsung-profit-likely-biggest-six-quarters-higher-chip-prices-2024-04-03/ Samsung's chip design and chip contract manufacturing businesses are still loss-making, analysts said. However, the chip division is expected to be profitable thanks to higher DRAM and...
  3. F

    CNN coverage of TSMC (interview with Lora Ho)

    Today on CNN 10, Will Ripley gives us a look inside the Taiwan Semiconductor Manufacturing Company, the world's largest producer of microchips that power everything from smartphones to cars to artificial intelligence applications...
  4. F

    Samsung unveils 3D DRAM plans at MemCon 2024

    https://semiengineering.com/chip-industry-week-in-review-28/
  5. F

    China blocks use of Intel and AMD chips in government computers

    https://www.ft.com/content/7bf0f79b-dea7-49fa-8253-f678d5acd64a China has introduced new guidelines that will mean US microprocessors from Intel and AMD are phased out of government PCs and servers, as Beijing ramps up a campaign to replace foreign technology with homegrown solutions. Lao...
  6. F

    SMIC reported to be developing 3nm internally

    https://www.techbang.com/posts/113767-smic-will-set-up-an-in-house-rd-team-to-start-rd-on-the-3nm It has been reported that SMIC has assembled a team to develop 3nm internally. Potentially, there could be a consideration of post-FinFET technology, such as CFETs. However, it is also widely...
  7. F

    TSMC to collaborate with SK Hynix on HBM4

    https://www.mk.co.kr/en/it/10939027 2024-02-07 17:50:18 Updated : 2024-02-08 10:50:52 SK Hynix and Taiwan's TSMC have established an 'AI Semiconductor Alliance'. SK Hynix has emerged as a strong player in the high-bandwidth memory (HBM) market due to the generative artificial intelligence...
  8. F

    Court sides with SK hynix against former HBM researcher's move to Micron

    https://koreajoongangdaily.joins.com/news/2024-03-07/business/industry/Court-sides-with-SK-hynix-against-former-researchers-move-to-Micron/1997008 A Seoul court sided with SK hynix in its attempt to ban a former engineer from working for rival Micron. The Seoul Central Court granted an...
  9. F

    ASML EUV source power information from SPIE 2024

    https://spie.org/advanced-lithography/presentation/High-power-EUV-light-sources-500w-for-high-throughput-in/12953-43#_=_ EUV lithography systems are now fully deployed in the high-volume manufacturing of leading edge semiconductor devices. In this paper, we review the performance of ASML’s...
  10. F

    Taiwan's defence ministry prepares for possible war

    https://www.reuters.com/world/china/china-steps-up-grey-zone-warfare-exhaust-taiwan-defence-report-says-2024-03-07/ TAIPEI, March 7 (Reuters) - China has stepped up grey-zone warfare against Taiwan, aiming to make the areas around the democratic island "saturated" with balloons, drones and...
  11. F

    imec study of EUV stochastic defects in wafer yield at SPIE 2024

    https://spie.org/advanced-lithography/presentation/Study-of-EUV-stochastic-defect-on-wafer-yield/12954-4#_=_ As semiconductor industry transitions to EUV lithography in advanced technology nodes, EUV stochastic defects play a significant role in chip yield degradation. Present yield models do...
  12. F

    Samsung seizes 2nm AI chip deal, challenging TSMC’s reign

    https://techhq.com/2024/02/samsung-seizes-2nm-ai-chip-deal-challenging-tsmc/ "In a notable turn of events disclosed during Samsung’s Q4 2023 financial report, the tech world buzzed with news of Samsung’s foundry division securing a prized contract for 2nm AI chips. Amid speculation, Samsung...
  13. F

    Samsung Reportedly Trials 2nd Gen 3nm Chips, Aims for 60%+ Yield

    https://www.trendforce.com/news/2024/01/22/news-samsung-reportedly-trials-2nd-gen-3nm-chips-aims-for-60-yield/ According to industry sources cited by South Korean media The Chosun Daily, Samsung has commenced the production of prototypes for its second-generation 3nm process and is testing the...
  14. F

    Winbond to transition to 16nm DRAM

    https://www.digitimes.com/news/a20240206PD224/winbond-16nm-dram-production.html Winbond is planning a transition to a 16nm DRAM process. Development has been ongoing for a while.
  15. F

    Samsung to open 3D DRAM research lab in US

    https://www.tomshardware.com/null/samsung-opens-next-gen-3d-dram-research-lab-in-the-united-states Samsung is currently in the process of developing next-gen 3D DRAM on American soil, says The Korea Times, according to its own industry sources. The lab for this next-gen 3D DRAM development is...
  16. F

    AMAT's patterning advantage over ASML?

    Looking over some patterning IP, I found these interesting two: US8084347(assigned to SanDisk then TSMC, but expired) and US8084310 (assigned to AMAT, expiring 2029). Either one it seems, or both in combination, would give a patterning advantage particularly for arrays of vias and pillars with...
  17. F

    Metal oxide EUV resist supplier embroiled in legal battle, challenge over license

    https://www.theregister.com/2024/02/06/us_research_body_sues_inpria/ "The Research Foundation for the State University of New York (SUNY RF) is suing a subsidiary of Japan's JSR Corporation over claims that photoresist materials developed by the foundation were commercialized and patented...
  18. F

    SMIC reportedly to produce 5nm Huawei chips despite sanctions

    https://techwireasia.com/02/2024/smic-huawei-defying-sanctions-leading-the-5nm-revolution/ As per the Financial Times report, SMIC will mass-produce 5nm chips designed by Huawei, and is building new production lines in Shanghai. For context, SMIC’s 7nm and 5nm chip production lines utilize...
  19. F

    Synopsys reports significant stochastic behavior for 2nm HiNA (~20 nm metal pitch)

    https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12495/124950W/Electrical-analysis-of-a-stochastically-simulated-2-nm-node-electrical/10.1117/12.2658780.short#_=_ The 21 nm pitch vertical M1 lines behaved worse than the 18 nm pitch horizontal M0 and M2 lines, due to being in...
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