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  1. S

    PD issues in AI SoC

    @ All , What are the possible issues at PD level for any AI Chip .
  2. S

    Design Verification issues for IoT / M2M ASICS

    @ All, Can we share views on issues we face or steps required to do Design and Verification or back end + Test of IoT and M2M (Machine to Machine) ASICs / SoCs Thanks, Paul
  3. S

    Power management techniques

    - Can somebody provide general outlook on various techniques for Power Management at System level ?- What are best in class techniques to optimize power at system level ? Thanks, Paul
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