You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
The problem of non-conventional approaches are 'software'. If we have super great compiler and runtime which are capable of break large operations into smaller OPs which perfectly fits to each accelerator(whatever accelerators are), removing all possible bubbles then it'll work. But can we? This...
We can see this in another way. In 2023, Samsung electronics reported that about 6B dollars were spent to buy Application Processors(from Qualcomm...etc). This means that Intel foundry will still lose money even if they get 20%(Samsung's smartphone share) of AP foundry share. In other words...
IFS was losing 4B in 2022(using their new financial model), even if they have in-house customer(Intel products). It's quite surprising because Intel products teams are the single largest leading edge silicon users in the world. Intel products revenue was almost 60B per year. Their modelled...
Still Intel expects 18A be a big and profitable node. It should be REALLY great then...I kinda see why they needed to introduce PowerVIA(BSPDN) earlier than competitors...
Intel's new disclose says followings.
(million dollars)
(2,100) Lower product profit driven by lower internal revenue
(411) Higher period charges related to excess capacity
when their products lost revenue 9,371 (from 57,038 to 47,667), foundry lost 2511. So without any further cost...
As long as there's value added, we can use everything. For example, in HBM(memory) manufacturing, stacking is used a lot even if price per bit goes up. They can use that because, AI companies are willing to pay A LOT.
In logic side, I think there will be a 'in-house design' era where large IT...
BTW, what's going to happen if we start using High NA EUVs later? Can we still get 800mm2~ish single chip? Since AI wants BF-chips, it's little concerning I guess..
I think Samsung runs one MPW for each full-node changes. 14nm, 8nm(10nm family), 5nm(7nm family), 4nm(Full node from 7nm. it was announced as 5nm half node at first, but updated later)
Cerebras uses BF wafer sized single chip(single big chip with spams of cores) and Groq and Tenstorrent uses high density racks(servers with spams of blades, cards...etc). It's quite ok for Groq and Tenstorrent to use Samsung anyway.
One of the problem Intel has is that there's more mobile customers than HPC customers. CPU and GPUs are high-volume HPC chips but Intel is unlikely to get orders from AMD who is in rear-view mirrors.
Intel was in chaos for a 6~7 years. So it's not really easy what's really happening there. If the leaker is correct then it's just same as what they did to Meteor lake(2023 Dec. launch, mobile only Intel 4).
Maybe they're doing this because they have reserved so much N3B capacity to hedge their...
This graph tells us a lot(Assuming that it's accurate). Look at the wafer capacity of Intel 4/3 which already got mass production chips(Meteor lake). Comparing its sheer volume to Intel 7(Which also has mass production chips), we can say that their manufacturing is not really recoverd. Maybe...
News seems busted. Actually the news doesn't look true to me. Samsung have been maunfacturing mining ASICs for a year, so It's hard to believe that their Galaxy Watch(Exynos W940, small chip) is running 0% yield. Maybe some insider saw failed experiement in certain lot?
It could still make sense, if they somehow mass produce GAA-powered Samsung LSI chips(Exynos?) and sell them to market. The real problem Samsung foundry had was not in press release(it's also problem though...), but in broken promises to their customers, even to their LSI counterpart. If foundry...
I was thinking about some micro-channel based ideas. Create small channels inside of the interposer to allow coolants directly into interposers or cold plates. I think i've seen it some IBM materials I think. Since these ideas require additional wafer processing, these could be foundries job...
We're not really shrinking, but stacking everything. Channels, dies and even power rails. Maybe it's time to think how we manage this thermals. Stacking helps us reducing ~10% ish power uses, but increase density a lot. We'll rely on a liquids...etc for a while, but I think it's time to...
It's really hard to summarize complex technological decisions into single word. Intel decided to wait for EUV methologies and throughput to increase, while using drastic new measures(COAG, Cobalt metals...etc), to increase densities using DUV. So Intel was risk taker of transistor manufacturing...
