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As many on this forum are aware, maximum theoretical logic density is often calculated by taking the (M2 pitch) X (M2 tracks for a four transistor NAND gate) X (CPP). From there we try to use correction factors to account any boundary scaling (for example Scotten using 10% area reduction from...
At IEDM23 we got to get a glimpse at the early enabling work for the big three’s CFET technology. One thing I found very interesting was the seemingly different research priorities.
Samsung in someways had simultaneously the most and least impressive showing. They showed off a CFET device with...
Thought the fine folks of semiwiki would enjoy seeing some lovely interviews that Ian made recently with GF CEO Tom Caulfield and intel Technology Development head Ann Kelleher.
There were some nice renders of Micron's US fab plans. It was also pretty funny (and painful) hearing the explanation of HBM.
As a side note I remember hearing a while ago that Micron JP and Boise do joint DRAM technology development. Does anyone have any idea what that even means. Does one or...
Question for all of those hard design/eda folks on semiwiki
Given the finlex libs vaguely look like the above image, I was wondering how common is it in modern chip designs for clock sensitive blocks for be on separate rows (ie above or below) non clock sensitive blocks? Or is it more common...
https://newsroom.lamresearch.com/3D-DRAM-architecture-proposal?blog=true
An interesting article to read through for those who haven't been keeping up with all the latest on 3D-DRAM process integration or architectures
Tokyo, April 18, 2023 – Hitachi High-Tech Corporation ("Hitachi High-Tech") today announced that it will construct a new production facility in Kasado Area of Kudamatsu City, Yamaguchi Prefecture, with a view to increasing production capacity of etching systems for its semiconductor...
At least in the case of Kioxia it would seem their fabs are a good bit taller than modern logic fabs. Fabs 2-5 look to be a similar height to TSMC's Fab 18 and Intel's D1X. Given these logic fabs are taller than prior generations of fab shells in order to accommodate the large size of EUV tools...
I recently learned that the first HKMG DRAM only entered HVM relatively recently, having scanned some IEEE papers from the early finFET era they just say that HKMG would make for stronger lower power DRAM (duh) and that it would require alot of work. More recent papers make a big deal of "DRAM...
IDEM and the VLSI symposium have given us a good amount of data to pour over for the node landscape from TSMC and intel in 2023/early 2024. Samsung having declined to give any details on the "in production" 3GAE that has "perfect yields" (their words not mine). I thought it might be nice if that...
One of the great benefits of being fabless has been the ability to not worry about process, and just use the best node for your product. If you are fabbing bleeding edge chips, since N7 TSMC has been the unquestioned leader of customer service and process. At 16FFL we saw close partners of TSMC...
Like Morris Chang, Robert Tsao also had a dream of creating a semiconductor foundry. Back when UMC was first founded though they had a harder time getting external contracts than TSMC due to the issues associated with IDM foundries and the small size of the fabless ecosystem at the time. As a...
For many years now further density improvements have been off of the back of fin depopulation. Ordinarily this would come at a large performance cost, but with new nodes better transistors offset this performance degradation with better transistors that are slightly stronger in spite of the...
While I am not sure it was intentional, UMC often would be a fast follower to TSMC, and before 28nm this worked out well for them as designs could be easily ported from TSMC nodes to UMC nodes. Once TSMC started accelerating away and UMC's nodes stopped being design compatible this model fell...
The other day I had a stimulating conversation with a colleague, and wanted to let the fine folks on semiwiki in on our little thought experiment. Before getting into the new process development scheme, first some background:
Across the 2000s and most of the 2010s intel pursued what they termed...
With N5/3 having a 9 track HP cell and a 5 track HD cell, and intel having a 5 track HP cell for i4 a few questions came to mind. With i3 having HD libraries, as well as "denser" libraries across the board, what is the minimum number of tracks that one can achieve with a finFET without BPR? We...
There has been much talk around how big of a change GAA is going to be for the eda/design ecosystems. There is also the thought that many folks are probably going to stick with N3 for a good while so they can avoid the worst of the N2 growing pains. I also remember seeing that Samsung said that...
