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Every so often we have a discussion about the compactness of a new process. You know, what does it mean to be a 2nm process when nothing is actually 2nm. Suggestions often include things like transistors per sq mm or the size of some key standard logic cells like NAND2, D-FlipFLop, and SRAM in...
Passing gates have at times been used to provide isolation between access transistors on DRAM. The rationale has been that a regular grid of gates promotes ideal lithography and if every 3rd gate is held "off" then the other 2 gates in the saddle are isolated as required.
The alternative...
Really giant. I suppose the optics involved just scan the mask for longer, with the same slit.
https://spie.org/a/69938
Highlights of the mask industry workshop on 6"x12" mask format for EUVL
Frank E. Abboud, Vice President Technology Development ,Intel Corporation.
Our mask industry has...
https://www.bnnbloomberg.ca/tsmc-drops-plan-for-chip-plant-after-reports-of-local-protests-1.1985581
Seems like this 2nm plant was not for the immediate future but still interesting that they got blocked on land use issues. That they gave up may lend weight to them using capacity elsewhere.
I've sampled some of these. Take your pick of computing topics - memory, superscalar, coherency, caching, pipelining, bandwidth, bus, .. - there are gems in this list on something you will be interested in.
https://sites.coecis.cornell.edu/isca50retrospective/
I'm curious how thick the water is. I was assuming a few microns but then I came across a 2008 document taking about a millimeter. I was thinking the lens "flies" low almost like an HDD head.
As expected, running fabs full blast at a loss in a downturn does not make your losses more sustainable than for your competitors who match your prices but reduce production:
https://pulsenews.co.kr/view.php?sc=30800028&year=2023&no=246255
A Starlith 1900i will have an NA of 1.35 at the wafer under water. However, at the input to the lens, focus on the photomask, what is the NA there? I found one mention of 0.75 but it was just an example, and that would seem to be a difficult number since it was state of the art at the wafer...
I recall a couple of years back Intel claiming price per transistor was still declining because the pricing curves showing most recent nodes at high prices were simply showing the premium of being new. When the node was in full production and no longer leading edge, the price would go down to...
Where would an inventor go to get a device structure fabricated in experimental quantity? At 40, 28, or 20 nm (the device functionality at small geometry is something to be proven)?
I would assume that this would be using something like an electron beam fab, and I found some of that on line...
A Rare Tour Of Microsoft's Hyperscale Datacenters
I hope some of you would find current DC builds of interest, and the article also discusses some of the changes that have occurred as we gained experience and scale. I work on building machines that go in there, and have toured that Gen5 site...
