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Fun to see the gaggle of politicians who voted against the CHIPs act, especially ones from Idaho, TX, and NY, now scrambling to take credit for it. Ted Cruz leads the pack of the credit-stealers. He should own his opinion and just say, I didn’t want this to happen.
Sorry 1.8M P60s. But I was really only focused on the Mate 60s Pros that use the homegrown Kirin 9000, fabricated at SMIC South.
https://www.reuters.com/technology/us-targets-chinas-top-chipmaking-plant-after-huawei-mate-60-pro-sources-say-2024-02-21/
The TechInsights report that SCMP is quoting from says only 1.8M Mate 60s last year (maybe that reflects running out of inventories of the SnapDragon 8+ , or a product transition). It could have 30M units over the life of the 60, but it sounds like it is EOL. And the Mate 60 Pro that was...
Thanks Fred. - that would mean that the Kirin 9000 numbers were even more anemic, only 1/3 of projections. Based on the numbers it sure seems like both yield issues and diversion of capacity to AI chips are limiting factors vs. the hype surrounding this “breakthrough“ SoCs. And Huawei is tamping...
Pretty good call @hist78 and @Jert. Saw this retrospective on Mate 60 / Mate 60 Pro volumes, in SCMP. Less than half of the hyped volume (I saw 30M another place when the 60 launched.
“The Pura 70 line is expected to generate global shipments of around 10.4 million this year, compared to the...
One other interesting dynamic I heard yesterday is that 90% of the training CPU cycles and hardware for generative AI is concentrated in 9 companies. Seems like it would be very hard to get a foothold in these 9 at any kind of scale, especially with several already developing their own chips as...
The OpenVino “support” chart below kind of highlights the challenge #2 I mentioned, as well as raising the question you highlight, “is it really a standard outside of Intel ?” It brings together 8 1/2 different hardware architectures, 8 of which are all Intel inference architectures. And where...
My view is that Intel has been struggling with 4 concurrent challenges:
1) Historically, the traditional Innovators Dilemma. The same force that enabled Intel (and to some degree AMD) to replace IBM mainframes and Sun servers in the server space with x86, thwarted their success in smartphones...
If we see leading edge AI models continue to progress the way they are going, with exponential growth in model parameter count, with reduced compute for a large percentage of the parameters (FP4, sparsity harvesting), we’re likely to see logic-in-memory approaches that offer lower power and less...
Definitely the least outrageous April Fool’s news article I saw this cycle. I immediately put this one in the possible bucket. Given the fake news social media environment we’re living in, I always look for multiple sourcing of any “news” in a posting. So I only confirmed the “joke” the same way...
We’re also living in a world where many poorer countries can no longer look to manufacturing as the playbook for becoming wealthier. Not everyone can “afford” to manufacture in the face of China and other mercantile producers that use their immense scale and industrial policy, including massive...
Yield, cost, profitability and scale are extremely important, especially in your “China creates an entire completely parallel semiconductor ecosystem” scenario. I just don’t see China building out a trillion dollar money losing ecosystem, especially when local governments, builders and many...
More Ascend 910Bs means far fewer Kirin chips due yield and capacity issues.
Exclusive: AI chip demand forces Huawei to slow smartphone production
https://www.reuters.com/technology/ai-chip-demand-forces-huawei-slow-smartphone-production-sources-2024-02-05/
But by then, TSMC is making the big profits on 3nm. And smartphones, CPUs and AI chips are riding down the next yield curve with them. It’s no fun to be a node or two back in lower volumes and higher costs for your end customers.
That‘s true, but if your yield for 5nm is 50% when the other guy’s is 90% for the same kind of chip, that’s a formula for losing money. And the yield learning curve is a function of scale and number of varied designs, etc. So SMIC / Huawei is never going to be ahead of foundries with higher...
That‘s just the patterning cost of extra steps. What about the yield hit ? Pretty sure that’s not factored in, and of course highly depends on die size as well as type of design and where the foundry is in the yield curve. I’m pretty sure that’s the place where TSMC excels, based on scale and...
The real question in my mind is what is the yield outcome and costs of all the extra steps ? If the eventual cost continues to be a 40-50% premium over comparable TSMC costs, what does that mean for end products using advanced processes ...
