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Search results

  1. G

    Essential ingredients for developing VIPs

    The last post Verification IP : Build or Buy? initiated some good offline discussions over emails & with verification folks on my visit to customers. Given the interest, here is a quick summary of important items that needs to be taken care of while developing a VIP or evaluating one. Hopefully...
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    Verification IP : Build vs Buy?

    Consumerism of electronic products is driving the SoC companies to tape out multiple variants of products every year. Demand for faster, low power, more functionality and interoperability is forcing the industry to come up with standard solutions for different interfaces on the SoC. In past...
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    Verification Futures India 2013 : Quick recap

    Verification Futures started off in 2011 from UK and in 2013 touched the grounds at India too. It is a one day conference organized by T&VS providing a platform for users to share the challenges in verification and for the EDA vendors to respond with potential and upcoming solutions. The...
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    Over-verification : an intricate puzzle

    For verification, it was an eventful week. DVCON 2013 kept everyone busy with record attendance at the sessions and by following the tweets & blogs that resulted from them. The major highlight of this year’s conference was release of the latest update to System Verilog standard, IEEE 1800-2012...
  5. G

    Evolution of the test bench - Part 2

    In the last post, we looked into the directed verification approach where, the test benches were typically dumb while the tests comprised of stimuli and monitors. The progress on verification was in linear relationship with the no. of tests developed and passing. There was no concept of...
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    Evolution of the test bench - Part 1

    Nothing is permanent except change and need constantly guides innovation. Taking a holistic view with reference to a theme throws light on the evolution of the subject. In a pursuit to double the transistors periodically, the design representation has experienced a shift from transistors à gates...
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    HANUMAN of verification team!

    While Moore’s law continues to guide innovation and complexity in semiconductors, there are other factors that are further accelerating it. From iPod to iPhone5 via iPad, Apple has redefined the dynamics of this industry. New product launches include one from Apple every year, equally...
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    Verifying with JUGAAD

    The total effort spent on verification is continuously on the rise (click here). This boost can be attributed to multiple reasons such as – - Rising complexity of the design further guided by Moore’s law - Constrained random test benches coupled with complex cross cover bins - Incorporating...
  9. G

    Communicating BUGS or BUGgy Communication

    A few decades back when the designs had limited gate count, designers used to verify their code themselves. With design complexity increasing, the verification engineers were introduced to the ASIC teams. As Moore’s law continues to drive the complexity further, IP reuse picked up and this...
  10. G

    Laws and Verification

    LAW means “a generalization that describes recurring facts or events in nature” and engineering is full of laws. Though laws are formulated for a particular aspect of engineering, most of these are widely applicable to parallel areas too. The idea here is to salute the heroes who articulated...
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    Verification claims 70% of the chip design schedule!

    Human psychology points to the fact that constant repetition of any statement registers the same into sub-conscious mind and we start believing into it. The statement, “Verification claims 70% of the schedule” has been floating around in articles, keynotes and discussions for almost 2 decades so...
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    Choosing the right VIP

    In past few months, while interacting with customers, I came across a couple of cases where the VIP played a spoilsport. In one case, the IP & VIP were procured from the same vendor during the early phase of standard protocol evolution. One of the key USPs of the product was this IP and the...
  13. G

    VIP : Changing landscape - Part 2

    In the last part we discussed about VIP and the changing landscape. While the increasing demand of VIPs would drive more participants to enter this space, there are significant challenges to come up with a decent VIP portfolio. </SPAN> Challenges for new entrants</SPAN> - Which...
  14. G

    Verification IP : Changing landscape

    For decades, EDA industry has been working out options to improve their offerings and ensure silicon success for the semiconductor industry. A few decades back, while the EDA giants were unknown, design automation was exercised individually in every organization developing a product. Gradually...
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    Constrained Random Verification and Simulators

    In response to my earlier post on CRV, Daniel Payne raised an interesting question on Semiwiki - "Is there any difference in choosing a VHDL, Verilog, System C or System Verilog simulator from Cadence, Synopsys or Mentor and then using the CRV approach”? Before answering this, let’s quickly...
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    Constrained Random Verification : A case study

    In continuation with the CRV discussion, here is a quick case study that walks through a verification project execution and the outcome: Constrained Random Verification : A case studyContinuing the discussion further, here is a case study where a performance intense core was verified from...
  17. G

    Constrained Random Verification + and -

    In the last decade, adherence to Moore’s law demanded ‘divide and conquer approach’ for developing SoC/ASIC. The design cycle now requires develop/procure IPs; build sub systems using them and integrate these sub systems further to realize the final product. Some IPs (Networking protocols...
  18. G

    Scoreboard in verification

    Recently while reviewing a test bench architecture with a group of verification engineers, an inveterate though interesting debate started. The engineer proposing the verification plan had ‘scoreboard’ as well as ‘checkers’ as two different components in his test bench. The debate was on the...
  19. G

    Trends in ASIC verification

    DVCON 2011 held at San Jose between FEB 28 to MAR 3 was quite a success. While UVM dominated the conference, the keynote by Walden Rhines was quite very interesting. The presentation, “</SPAN>From Volume to Velocity</SPAN></SPAN>” touched upon the what’s going on in verification for past few...
  20. G

    Gate level simulations - A necessary evil

    3 part series discussion the NEED for GLS and why is it considered EVIL. The final wrap up with some good practices. Part 1 - siddhakarana: Gate Level Simulations : A Necessary Evil - Part 1 Rising complexity, tightening schedules and ever demanding time to market pressure are pushing the...
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