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Search results

  1. Daniel Payne

    Ultra Librarian and Zuken Work Together to Create a Seamless User Experience for PCB Design

    Ultra Librarian is now directly integrated within eCADSTAR, making it easier than ever to access parts during the design process. Rochester, NY (October 27, 2020)—Ultra Librarian®, (ultralibrarian.com) the world's largest free cloud-based CAD library provider, announced its collaboration with...
  2. Daniel Payne

    EDUCATIONAL : Verilog-A tutorial

    Thanks for sharing the link to the four YouTube videos on Verilog-A. The only nit is that the right side of the YouTube video has noise in it, likely an artifact of some conversion process.
  3. Daniel Payne

    Are Stretched Resources Limiting TSM's Growth

    Here's a list of MEMS foundries, https://en.wikipedia.org/wiki/List_of_MEMS_foundries. Notice how fractured the marketplace is. The process nodes for MEMS does not requirer bleeding edge nm scales, so TSMC has no real advantages over these hyper-focused suppliers.
  4. Daniel Payne

    DVCon Europe Announces two extra Keynotes and full Technical Program

    Virtual event incorporates Virtual Experience Rooms for easy networking Munich, Germany – 6th October, 2020 - The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced two new keynote speakers and a full technical...
  5. Daniel Payne

    Equivalent ASIC and FPGA designs

    Dynamic power usage in an FPGA for unused gates would also be minimal. There are many ASIC service companies that can provide you a quote for migration, and explain the subtle things to look out for.
  6. Daniel Payne

    Equivalent ASIC and FPGA designs

    A1: Yes, an FPGA design can be migrated to an ASIC. The physical IC layout of an ASIC and FPGA are totally different, so there's no concept of layout re-use between the approaches. A2: You choose an FPGA array size based upon the size of your design, with a goal of leaving as few un-used gates...
  7. Daniel Payne

    Number of worldwide tapeouts

    The foundries often publish charts showing the mix of revenue per process node, and some of the EDA vendors will chart out the number of tapeouts on their specific tools. Source: Synopsys
  8. Daniel Payne

    Save Arm - Arm is being sold to Nvidia - Help Stop it!

    Arm has no motivation to license its crown IP in the CUDA cores, because that is their competitive advantage in the marketplace.
  9. Daniel Payne

    Save Arm - Arm is being sold to Nvidia - Help Stop it!

    I signed the petition, because ARM needs to remain neutral and not compete with it's customers.
  10. Daniel Payne

    New Release of Easy-PC PCB Design Suite Includes Over 50 New Customer Requested Features and Is Part of a Summer Promotional Offer Ending September

    New Release of Easy-PC PCB Design Suite Includes Over 50 New Customer Requested Features and Is Part of a Summer Promotional Offer Ending September 30th Upgrade from any version of Easy-PC to version 24 for only $117, with new purchases starting at $457. Tewkesbury, UK (September 16, 2020)...
  11. Daniel Payne

    PRO DESIGN Unveils New Xilinx® Virtex® UltraScale+ VU19P-Based Product Family of Prototyping Platforms

    Munich, 16 September 2020 - PRO DESIGN, veteran in the E²MS industry and leading supplier of high-speed ASIC and SoC verification platforms, launches today its new proFPGA UNO, DUO and QUAD systems based on the latest Xilinx® Virtex® UltraScale+ VU19P FPGA technology. These state of the art...
  12. Daniel Payne

    Intel Launch Event

    I'll be interested to see how this new 11th Gen Intel Core processor holds up against the ARM-based CPU from Apple.
  13. Daniel Payne

    Will EDA Evolve into a Foundry/Platform/AI/ML Model? Ramifications?

    Arthur, the closest thing to quick chip design today would be with the FPGA vendor tools, IP and flow: Xilinx (Vivado Design Flow) and Intel (Intel HLS Compiler). With an FPGA the designer is removed quite a bit from the physical Implementation, yet they still have to choose their IP building...
  14. Daniel Payne

    Will EDA Evolve into a Foundry/Platform/AI/ML Model? Ramifications?

    Arthur, what you propose is already being done by IC Design Services companies. In the past, many of the EDA companies also had an IC Design Services department, and Cadence was the most noticeable in building up what their Spectrum Services Group. There are probably 100+ IC Design Services...
  15. Daniel Payne

    DVCon U.S. 2021 Announces Call for Extended Abstracts

    Gainesville, FL – August 12, 2020 - The 2021 Design and Verification Conference and Exhibition United States (DVCon U.S.), sponsored by Accellera Systems Initiative, announces its call for extended abstract proposals. The submission site for extended abstracts is open through August 24. The...
  16. Daniel Payne

    ISQED'21 - Call for papers

    Submission Deadline: Oct. 2nd, 2020 About the Conference A pioneer and leading interdisciplinary conference, the 22ndInternational Symposium on Quality Electronic Design (ISQED'21)accepts and promotes original and unpublished papers related to the topics shown below. ISQED'21 theme is AI/ML&...
  17. Daniel Payne

    Will TSM ever become an analog foundry?

    TSMC will certainly fab your analog IP and have been doing so for many years now. https://www.tsmc.com/tsmcdotcom/PRListingNewsArchivesAction.do?action=detail&newsid=STSTST&language=E https://www.tsmc.com/english/dedicatedFoundry/oip/s010454.htm...
  18. Daniel Payne

    What Ecosystems to Dominate AI/ML, Hardware and Software?

    Chris Rowen is quite knowledgable about AI/ML and has many resources listed at his site Cognite Ventures, http://www.cogniteventures.com/the-cognite-300-startup-poster/. He tracks and categorizes some 350 AI/ML companies, and is often speaking at conferences on the topic.
  19. Daniel Payne

    An open source PDK for 130nm process node

    Stefan Wallentowitz, FOSSi Foundation Tim Ansell, Google
  20. Daniel Payne

    2D Metal to Replace Silicon in Memory??

    The article states that to read the data requires use of a magnetic field, but they don't provide any details for integrated circuitry that small at the nanometer level. My take is that this is pure research with no application. Just writing data is only half of the job of a memory circuit.
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