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Search results

  1. T

    VLSI Design Methodology Development Webinar Replay and Follow up Q&A!

    Omer: Thanks for the comments about the book! Pearson Publishing recently added a set of presentation slides to the web site for the book. I created a slide for each figure in the book, with supporting comments. The slides for each chapter are compressed into a .zip file and available for...
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    VLSI Design Methodology Development Webinar Replay and Follow up Q&A!

    Randy: Thanks for your comments and questions! Alas, due to limitations on the length of the text, some topics only received a brief introduction. - high-level synthesis (HLS) The text does go into some detail on the distinctions between sequential and RTL coding styles in current...
  3. T

    Lithographic Patterning using Tilted Ion Implantation (TII)

    To achieve an aggressive lithographic pitch in advanced process nodes, foundries have employed self-aligned double patterning (SADP), using sidewall spacers as the final masking layer. In the future, another iteration of this method will offer quad patterning, or SAQP. The team at UC-Berkeley...
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    The RISC vs. CISC debate Redux

    I recently came across an interesting technical article, with a current interpretation of the infamous RISC vs. CISC instruction set architecture debate, which has been ingrained in the computer science field for over 25 years. A link to the article is here. The paper provides a good...
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