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  1. F

    Could Pat Gelsinger be reinstated as Intel's CEO?

    Seems the board would have to go for that to happen.
  2. F

    Intel Foundry Fails To Impress Once Again, 18A Process “Yield Rates’ Are Reported To Be Only 10% Making Mass-Production Impossible FROM wccftech

    Assuming Broadcom was a customer, it would have received PDK 1.0: https://hwbusters.com/news/intels-18a-faces-challenges-with-broadcom-while-20a-plans-for-arrow-lake-are-canceled-for-foundry-customers/ So PM's comment suggests they got the bad results with an older PDK.
  3. F

    Intel Foundry Fails To Impress Once Again, 18A Process “Yield Rates’ Are Reported To Be Only 10% Making Mass-Production Impossible FROM wccftech

    Obviously D0 is not a steady number, it can go up or down.
  4. F

    Intel Corporation to Participate in Upcoming Investor Conferences

    I thought this meant that Intel products would be the main driver of foundry revenue in the short term.
  5. F

    Intel Corporation to Participate in Upcoming Investor Conferences

    Two statements from Naga give reason to be wary: 1. "And 18A, our biggest customer for the next two, three years is still Intel products," 2. "Now it is about going through the remaining yield challenges, defect density challenges, continuing to improve it, improving process margin and getting...
  6. F

    Intel 18A "too good" but design lags

    I just read Naga Chandrasekaran saying that 18A still had defect density challenges and milestones to achieve. https://seekingalpha.com/article/4742201-intel-corporation-intc-ubs-global-technology-and-ai-conference-transcript
  7. F

    TSMC's N2 process has a major advantage over Intel's 18A: SRAM density

    He's using a formula 0.667/density (Mb/mm2) to give SRAM cell size, but it's definitely not a fixed formula.
  8. F

    TSMC starts equipment installation for 2nm fab

    No high-NA because there is stitching. Moreover, the EUV community knows (but doesn't like to announce widely) that high-NA requires a different EUV mask substrate than the 0.33NA.
  9. F

    Intel 18A "too good" but design lags

    Intel 18A has two sets of interconnects (backside and frontside) which have to be separately aligned and patterned. TSMC A16 would be the same. https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
  10. F

    Inside Intel’s Lunar Lake: A Promise That Became a Problem

    TSMC doesn't supply the DRAM that is bundled into the packaging. It just meant relying on TSMC is unfavorable for Intel's cost structure.
  11. F

    Inside Intel’s Lunar Lake: A Promise That Became a Problem

    郭明錤 (Ming-Chi Kuo) Nov 5, 2024 Intel has recently announced that after Lunar Lake (LNL), it will discontinue integrating DRAM into CPU packaging. While this news has caught public attention recently, people working in the PC industry have known for at least six months — according to Intel’s...
  12. F

    Intel 18A "too good" but design lags

    Got this from X but too interesting to let it go by: "The design service and design enablement is still fairly weak at Intel right now, but the technology is just way too good." He noted Samsung's MOL had issues, but no comments on TSMC.
  13. F

    ASML provides updated view on market opportunities at 2024 Investor Day meeting

    That's funny, since they brought up the necessity of double patterning EUV at 5nm, triple patterning at 3nm, and quadruple patterning at 2nm. With 0.55 NA, stitching also forces loosening of minimum pitch, entailing multipatterning.
  14. F

    Japan’s Rapidus to Receive First EUV in mid-December, with ASML Planning Service Center Nearby

    Rapidus plans to focus on smaller clients who can't afford the new 2nm technology. https://www.trendforce.com/news/2024/04/26/news-rapidus-focuses-on-small-clients-diversifies-into-japan-to-mitigate-us-geopolitical-risks/
  15. F

    The Huawei-TSMC-7nm chip thing doesn't make much sense

    Without thinking too much about it, the cost is easily a top reason. TSMC 7nm is likely (still) cheaper than SMIC 7nm at this point, although SMIC N+2 probably is better than where it started a few years ago. I suppose the teardowns would have to confirm it one way or the other, but the use of...
  16. F

    Intel CEO optimistic about CHIPS Act’s future after trading texts with JD Vance

    According to Reddit the officials are delaying payments because Intel is not giving them required information on its manufacturing road map.
  17. F

    Intel CEO optimistic about CHIPS Act’s future after trading texts with JD Vance

    According to the PMT: "The award amounts are subject to due diligence and negotiation of a long-form term sheet and award documents and are conditional on the achievement of certain milestones and remain subject to availability of funds. After the PMT is signed, the Department begins a...
  18. F

    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements

    Must N2 be a pitch shrink from N3?
  19. F

    Intel CEO optimistic about CHIPS Act’s future after trading texts with JD Vance

    https://abc6onyourside.com/news/local/intel-dropped-from-the-dow-and-still-without-chips-act-funding-nvidia-jones-industrial-average-department-of-commerce-ohio-one-new-albany-central-ohio-growth
  20. F

    TSMC hints at its EUV tool count to the Register

    "TSMC carefully evaluates technology innovations such as new transistor structures and new tools and considers their maturity, cost, and benefit to customers before deploying them to volume production," the chipmaker told The Reg. "As we disclosed at our 2024 Technology Symposiums earlier this...
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