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Search results

  1. Daniel Payne

    Daniel Nenni on Broken Silicon / MLID - 5/13/24

    The host pronounces the world Silicon unlike what every semiconductor professional uses, so I cannot bear to listen to his podcast.
  2. Daniel Payne

    3 New Groundbreaking Chips Explained: Outperforming Moore's Law

    Uh, her LinkedIn profile has no company name mentioned, at the top it says Austria, but then it also says Munich area. Her education was in Russia. A more credible person would certainly list the name of their company,, and the list of chips and foundry nodes that they have designed. She does...
  3. Daniel Payne

    Big Tech focuses on in-house chips: Here's what you need to know

    Nice tech story, however these non-technical communicators are often unable to distinguish between designing an SoC versus building or fabrication of the SoC. AWS will design their Graviton4 chips, while TSMC will build or fabricate the SoC. The video segment was set in a facility where...
  4. Daniel Payne

    Arm is a "circuit designer"?

    I don't have a subscription to the WSJ, so couldn't read the article. SoftBank paid way too much money for Arm at $32B in 2016, so let's see what the IPO raises.
  5. Daniel Payne

    Arm is a "circuit designer"?

    In the 1970s my title at Intel was Circuit Designer, which at that time meant that I designed DRAM chips at the transistor level. Another job title was Logic Designer, and they worked with gates. Eventually with languages like Verilog and VHDL, the title was RTL Designer. Newer titles are SoC...
  6. Daniel Payne

    ChatGPT: What is SemiWiki?

    I also asked ChatGPT, "Who is Daniel Payne", and it produced so many mistakes that its replies are quite untrusted. Why the industry has fallen for ChatGPT is a bit mystifying to me, with so many fabrications in the answers.
  7. Daniel Payne

    Intel cuts pay to support the dividend

    I worked at Intel from 1982 to 1986 when they: Froze all hiring Froze all pay raises Gave everyone a 10% pay cut Finally, asked everyone to work 2 hours/day extra, without pay In those four years about 25% of the company simply quit, including me, so I joined my first EDA company in 1986. It's...
  8. Daniel Payne

    Can Bitcoin mining centers be used for blockchain for other purposes?

    Bitcoin mining typically uses many GPU servers to perform mathematical calculations in order to earn a new bitcoin. When a bitcoin is deposited into an account, then it is stored in a distributed ledger known as blockchain. So bitcoin is a virtual currency, while blockchain is a software storage...
  9. Daniel Payne

    Amazon's Graviton Chips, Is Amazon changing the game?

    A quick Google search of SemiWiki finds "Graviton" mentioned 249 times, so yes, AWS and other systems companies are designing their own chips to accelerate domain-specific workloads, because CPUs and GPUs aren't efficient enough.
  10. Daniel Payne

    How are gate counts measured?

    The Inverter, or NOT gate only has 2 transistors, so would count as half a gate. The CMOS XOR gate can have 12 transistors, so would count as 3 gates. Transistor count is quite precise, and not open to interpretation. Some engineers see ICs as collections of transistors, like me, because I was a...
  11. Daniel Payne

    How are gate counts measured?

    Logic synthesis tools require a cell library, and each cell has an area assigned to it, but the results of synthesis depend on how you control the tool. If you ask for maximum speed, then synthesis may return a higher gate count along the critical paths, trading off more area for higher speed...
  12. Daniel Payne

    Transistor count calculation problem

    Some chip design companies openly state what their total transistor count is, so it's mostly bragging rights, and they often round to the nearest billion transistors for the largest SoC designs. In the early days of ASICs and FPGA designs, the companies would often cite Gate count, where a Gate...
  13. Daniel Payne

    What Samsung’s Return to U.S. Chip Manufacturing Means For the Economy

    Taylor, Texas reminds me of Aloha, Oregon, because Intel's first Oregon fab was placed in the tiny community of Aloha in 1974, for exactly the same reasons, tax incentives.
  14. Daniel Payne

    Is single-die DRAM gone in favor of stacked-die?

    Yes, I'm amazed at the thermal challenges for stacked chips, what an engineering effort to keep these stacked die systems operating reliably.
  15. Daniel Payne

    Is single-die DRAM gone in favor of stacked-die?

    Several companies have announced stacked DRAM chips: https://arxiv.org/abs/1809.08828 https://www.vikingtechnology.com/dram-modules/dram-memory-stacking/ https://www.slashgear.com/samsung-12-layer-3d-tsv-stacks-12-dram-chips-in-the-same-space-as-8-07594321/...
  16. Daniel Payne

    Making Fat Man's Suits Out of Thin Man's Cloth: can leading-edge equipment fabricate trailing-edge die?

    The average cost of a 180nm mask set is $100,000.00, however that same IC layout, but using 40nm masks will cost you $900,000.00. https://anysilicon.com/semiconductor-wafer-mask-costs/ The gate oxide is thinner for 40nm versus 180nm, which then effects the Vt of the transistor. So moving from...
  17. Daniel Payne

    Making Fat Man's Suits Out of Thin Man's Cloth: can leading-edge equipment fabricate trailing-edge die?

    Good point. The DRC rule deck grows by several X as you move down each smaller process node, so that's an interesting question to run a 180nm mask set on a 40nm process. I'm not sure that it would pass the DRC and ERC. Certainly the timing would change, because the smaller nodes have higher...
  18. Daniel Payne

    Making Fat Man's Suits Out of Thin Man's Cloth: can leading-edge equipment fabricate trailing-edge die?

    Each foundry process has a Process Design Kit (PDK) that is unique, and migrating from 180nm to a smaller process node requires engineering work like: functional simulation, logic synthesis using a new cell library, buying and integrating new 3rd party IP blocks, floor planning, standard cell...
  19. Daniel Payne

    Name for dice on a wafer that are intentionally different than the others

    Good eye, the handful of different die are there for testing purposes to make precise measurements about that wafer. On the test die they can more easily and efficiently measure IV curves, junction leakages, ESD breakdown voltages, P vs N channel conductance, resistivity of interconnect, etc.
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