Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?search/239641/&c[users]=Scotten+Jones&o=date
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Search results

  1. S

    Intel's Foundry Business discloses a $7B operating loss

    What gap? I have done a ton of modeling of Intel over the years and confirmed/correlated results to published and private numbers. If a fab has a capacity of 100K wpm and is running 50K that is called utilization and it varies for all fabs, it is fully factored into my modeling. And while Intel...
  2. S

    Intel's Foundry Business discloses a $7B operating loss

    He said Intel has ~200k wpm starts, if that is correct their Fab utilization isn't good because they have a lot more capacity than that and they are adding more all the time.
  3. S

    Intel's Foundry Business discloses a $7B operating loss

    With respect to wafer cost the only yield that matters at all is line yield in the fab and everyone is in the high ninety percentiles. If you talk about die cost then die yield comes in and that is where Intel struggled at 14nm, and 10nm. Reportedly i4/i3 die yields are pretty good.
  4. S

    Intel's Foundry Business discloses a $7B operating loss

    I have actual numbers for 18A pitches, I can't publish them but I can say that 18A high density cell transistors per mm2 are slightly higher than TSMC 5nm but lower than TSMC 3nm. To even catch up to TSMC 2nm, Intel 14A would need a big density jump and this is during a time when density jumps...
  5. S

    Intel's Foundry Business discloses a $7B operating loss

    When comparing wafer costs there are two components, one is process cost and the other is fab cost. Intel 10/7 processes are very expensive processes compared to TSMC 7nm even if run in the same fab. Intel fabs are generally in higher cost countries plus Intel has some Intel specific cost...
  6. S

    Intel's Foundry Business discloses a $7B operating loss

    This is an interesting slide: - Performance/watt - I agree with their ratings. - Density - I don't agree with, TSMC is way ahead of 18A, maybe Intel could catch up at 14A but it would take a huge jump. - Wafer cost - surprisingly, I was just looking at wafer cost and through 18A I think they are...
  7. S

    The desperate battle for 2 nanometers will heat up next year

    "The cost of 2nm chips is very high. Research institutions pointed out that compared with 3nm, the cost will increase by 50%, and the single cost of each wafer will climb to US$30,000; therefore, the first batch of adopters will still be smartphone chips. Customer—Apple." When 3nm was still in...
  8. S

    Updating our current logic density benchmarking methodologies

    "As many on this forum are aware, maximum theoretical logic density is often calculated by taking the (M2 pitch) X (M2 tracks for a four transistor NAND gate) X (CPP). From there we try to use correction factors to account any boundary scaling (for example Scotten using 10% area reduction from...
  9. S

    How is backside power really done?

    The connection is from the side just like for the Power Via. "As a side note why do you think that AMAT and intel have a different definition of what BPR is from IMEC? The engineers from both firms are far from dummies, and they both contribute to IMEC. The difference in opinion and definition...
  10. S

    How is backside power really done?

    Imec tells me the AMAT diagram you used is incorrect with respect to BPR and it connects from the side, not up through metal 0.
  11. S

    How is backside power really done?

    My understanding is the process is: 1) Transistor formation and front side interconnect formation on the front of the device wafer. 2) A carrier wafer is bonded to the front of the device wafer. 3) The wafer pair is flipped over and most of the device wafer is removed from the back. 4) Through...
  12. S

    Will VTFET become the new chip technology?

    We are running 3nm now with 2nm (20A) due 2024 to 2026 depending on version and company. Samsung has talked about 1.4nm in 2027 based on a Horizontal Nanosheet with more sheets. My projections are 10A around 2029 based on a CFET, with 7A, 5A, and 3A CFETs to follow. Finally around 2037 we get...
  13. S

    Will VTFET become the new chip technology?

    High density logic cells in TSMC 3nm are just under 300MTx/mm2.
  14. S

    Will VTFET become the new chip technology?

    Aluminum for what, are you talking Buried Power Rail (BPR) because Al won't survive the temperatures or meet the electromigration requirements. If you are talking Backside Power Delivery that is copper and it is done at the end of the process flow.
  15. S

    Will VTFET become the new chip technology?

    The authors are a bunch of academics, it is an interesting intellectual exercise but I would be shocked if this ever saw the light of day.
  16. S

    Will VTFET become the new chip technology?

    It not quite 2x density due to interconnect requirements but it is a big jump. 2D gives a big jump in CPP and therefore cell width, and CFET gives a big jump in cell height by doubling up the transistors and eliminating the horizontal n-p spacing. My estimate is 1,500 MTx/mm2 in 2037.
  17. S

    Will VTFET become the new chip technology?

    Do you have a reference for that demonstrator, I have never heard of that and never heard/seen anyone talk about it and I am very plugged in to that community.
  18. S

    Will VTFET become the new chip technology?

    As is CFET and both Intel and TSMC have published on it extensively and both have shown slides with CFET as a post HNS option. Neither has talked about VTFET.
  19. S

    Will VTFET become the new chip technology?

    My own, I have been analyzing this path for many years, I have a presentation of over 60 slides that walks through the whole path and has been shared with/reviewed by a select group of experts.
Back
Top