Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?search/238975/&c[users]=Fred+Chen&o=date
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Search results

  1. F

    5 things you should know about High NA EUV lithography

    HS: understood. Checking the most recent CAR (probably more mainstream) literature, more or less the same trend toward reported sizing dose being higher, quite often significantly, than 30 mJ/cm2...
  2. F

    5 things you should know about High NA EUV lithography

    They had doses as high as over 80 mJ/cm2 here https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12957/129570V/Patterning-optimization-for-single-mask-bit-line-periphery-and-storage/10.1117/12.3010934.full#_=_ when MOR was used.
  3. F

    5 things you should know about High NA EUV lithography

    ASML did report on NXE:3800E getting >500W (but <505W): https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12953/129530V/High-power-EUV-light-sources-500w-for-high-throughput-in/10.1117/12.3010463.full#_=_ But TSMC earlier talked about pellicles not surviving long enough at 400W...
  4. F

    Semiconductor equipment maker ASML ships second 'High NA' EUV machine

    Some defects already visible from the tweeted image lol
  5. F

    5 things you should know about High NA EUV lithography

    The higher NA only improves the resolution of the so-called aerial image (image in space) not the actual resist image. The resist image contrast is limited further by photoelectrons, which can travel as far as 15 nm (in one direction) in one evaluated resist. They also didn't mention that in...
  6. F

    imec study of EUV stochastic defects in wafer yield at SPIE 2024

    Just read this paper, it turns out they are calibrating to previous papers' assumptions of defect density, but the trends they got were as expected.
  7. F

    Japan chipmaker Rapidus opens arm in Nvidia's backyard from Nikkei Asia

    Yes they hope to do single-wafer processing: https://www.eetimes.com/rapidus-ceo-chasing-single-wafer-processing-dream/
  8. F

    America’s Big Chipmaking Blunder

    They shouldn't let Bloomberg talk tech. They actually think 2D layers are being used.
  9. F

    US lawmakers angry after Huawei unveils laptop with new Intel AI chip

    It should be a big deal, this is Meteor Lake, with all the advanced chiplets.
  10. F

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    EUV had to be bought and subsequently used before the data was in, apparently. About the costs, some references below. Keep in mind, EUV resists are many times more expensive than DUV resists.
  11. F

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    I am not sure that is significantly the case, since EUV didn't get on all layers, especially 7nm. DUV double patterning still cheaper than EUV. On 5nm, the cost overall still went up since there was EUV and DUV multipatterning. I think there is still a common misconception that resolution is...
  12. F

    EUV mask absorber issue

    In particular, the wavelength dependence of fading is more severe with low-n: https://www.spiedigitallibrary.org/conference-proceedings-of-spie/11854/2600931/Simulation-of-polychromatic-effects-in-high-NA-EUV-lithography/10.1117/12.2600931.short#_=_ EUV is not just 13.5 nm but practically...
  13. F

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    You assumed EUV got you out of multipatterning, but that is not the case, even for High-NA (i.e., stitching of multiple exposures).
  14. F

    EUV mask absorber issue

    At this year's SPIE, there are indications current EUV masks have problems with the Ta-based absorbers, leading to image fading. Image fading has been covered in two papers...
  15. F

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    https://www.spiedigitallibrary.org/conference-proceedings-of-spie/browse/SPIE-Advanced-Lithography/2024#_=_
  16. F

    Huawei Patent Shows 6x Multi-Patterning Surpassing EUV Resolution Without EUV

    High-NA EUV could very well be a bad decision. There is no High-NA EUV print data. But we have enough information from existing EUV to show even that was questionable.
  17. F

    TSMC retains 2024 revenue view in sign of limited impact of earthquake

    Barclays was quoting TSMC but even with that preliminary estimate, it would not affect the full-year revenue which is much larger.
  18. F

    Will Intel Foundry Break-Even Before 2028?

    If Intel had to do all its Intel product 4, 3, 20, 18A, 14A tiles in-house, there wouldn't be enough capacity for foundry. So they had to outsource to TSMC. But it's doubtful they have the capacity for the same customer load as TSMC. There was a report that one customer did pay ahead for...
  19. F

    TSMC retains 2024 revenue view in sign of limited impact of earthquake

    TSMC assessed $60 million impact, but this is within the range of their annual revenue estimate. https://www.asiafinancial.com/tsmc-predicts-60m-hit-from-taiwans-biggest-quake-in-25-years
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