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Search results

  1. S

    Intel to Provide Updates on Foundry Business and Process Roadmap at IFS Direct Connect

    And I thought this time Intel would indeed grow the humbleness needed to run a foundry service... Seems I was wrong.
  2. S

    AMAT's patterning advantage over ASML?

    Self-aligned litho was a hype when I was in litho more than a decade ago. Seems it did not live up to it's promise even for very regular structures like NAND flash.
  3. S

    Intel Delays its Ohio fabs

    Indeed, if you have the full mask set data you can derive the full functionality of the design from it; it's called 'circuit extraction'.
  4. S

    TSMC cuts prices by 10% for its manufacturing process without warning. Senior executive reveals surprising secrets

    Before the chip squeeze during COVID TSMC did revise their prices regurlarly and they always went down. The price hike during that time has been the only exception I know of and surprised all in the field I know. More recent nodes typically get more price decrease even in relative terms (e.g. %)...
  5. S

    Exploring CPU Pipeline Depths: What's the Deepest Pipeline in Modern CPUs?

    BTW, Chips and Cheese is a site where you should be able to find a lot of the nitty gritty details on CPU architectures.
  6. S

    RISC-V technology emerges as battleground in US-China tech war

    Nice thing about open source stuff is that it does not really matter what is actually written in the standards, just how people commonly use it. E.g. like Linux following (in the beginning) POSIX mostly but not all.
  7. S

    Intel officially drops High-NA EUV for 18A production

    PS: forbidden pitches is not EUV specific; it's consequence of dipole illumination.
  8. S

    Primary contributors to wafer fab cycle time (which process steps?)

    Problem is that a semiconductor fab is not one long chain of machines after each but that the same tools are used for different steps in the processing of a lot. And these are not only wafer processing tools but alos metrology like CD-SEM, ellipsometry, etc. Problem is that the cycles in between...
  9. S

    How to develop EUV photoresists without an EUV machine?

    I have been working @ imec in the lithography group. Typically resist development starts on so-called small-field litho machines at sites like imec. These machines have a much smaller projection field than production machines but can already be used for resist development. Sometimes these...
  10. S

    Intel taping out 18A

    In semiconductors everything is about yield. If you do your own multi-foundry chiplet design and have a yield problem it's your own problem to solve. If you use a foundry provided chiplet solution they see yield problems as a problem for them to solve.
  11. S

    MVP

    555-timer
  12. S

    FPGAs must die. Cut EUV funding!

    As far as I know throughput of maskless ebeam is in hours/days per wafer rather than wafers per hour; especially for resolutions for which EUV is used.
  13. S

    Testing the bounds of loyalty for TSMC's inner circle

    You seem to confuse Trademark law with Copyright or Contract law. Wether you protected other IP or not before does not impact in any way how you can protect new unrelated IP.
  14. S

    Intel earnings announcement - gloomy 2023

    If most people are thinking that, it's often the right time to buy a stock indeed...
  15. S

    Maskless lithography

    Yes, I also remember this paper, I think it was from TSMC. If I remember correctly this was based on the MAPPER lithography machines that were on development at that time. The plan was to use an array of hundreds (if not thousands) tips as e-beam generators. It was fascinating technology but I...
  16. S

    Back of Envelope Wafer pricing based on TSMC Arizona Numbers

    Also don't forget that most equipment has support contracts of around 20% annual cost of original price for the equipment and that wafer manufacturing also involves high cost chemicals consumables like photosensitive resists, CMP slurries, etc
  17. S

    High-NA might be last-gen litho

    Next to higher NA I thought ASML was also still looking at lower wavelength. Is thiat now officially from the table ?
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