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Search results

  1. F

    Samsung 5LPE vs 7LPP - no pitch shrink!

    Reviewing the cell heights, it is apparent that Samsung's 5LPE adds a couple more track options to 7LPP but there is no metal or gate pitch shrink. In fact, for 5LPE "HD" is actually widened to 7.5 tracks (from 6.75 for 7LPP), while "UHD" is 6 tracks. It looks like it could be more appropriately...
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    why EUV instead of 157 immersion?

    Many have answered already, correctly indicating the 157 nm material issues. EUV offered the promise of a return to higher 'k1', which would have been 'easier', more conventional lithography. This is calculated by feature size x NA/wavelength, and is higher with the much shorter wavelength of...
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    A Survey on Reliability of DNN Algorithms and Accelerators

    NNs supposedly are more robust and therefore in less critical need of the usual guaranteed reliability.
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    EUV Shot Noise Impact on 7nm
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    EUV Shot Noise Impact on 7nm

    Hi Daniel, Thank you for your feedback. I am in fact preparing an article on LI which will show an effective way to visualize the recently published stochastic defects. Indeed, insufficient dose is a key factor, although the resist also plays a significant part. When it's online, I'll post the...
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    EUV Shot Noise Impact on 7nm

    The edge placement of line ends is also affected by photon shot noise. This can be considered by a fairly simple calculation: This also has an effect on the gap between line ends (tip-to-tip). Line cutting...
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    EUV was never going to be single patterning

    A discussion with Moshe Dokejsi reminded me back to this topic. Given that the illumination slit shape on the reticle is an arc, the actual illumination angle is rotated azimuthally through the arc. So in the slit center, your illumination may be optimized for 36 nm pitch, but at the edge...
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    Localized and cascading secondary electron generation as causes of stochastic defects

    Open Access: Localized and cascading secondary electron generation as causes of stochastic defects in extreme ultraviolet projection lithography Hiroshi Fukuda J. of Micro/Nanolithography, MEMS, and MOEMS, 18(1), 013503 (2019). Localized and cascading secondary electron generation as causes of...
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    Hydrogen-induced blistering of Mo/Si thin film multilayers Hydrogen is the most insidious element in thin film processing. In this case, we have blistering of what's supposed to be an atomically smooth optical surface. Hydrogen is mostly trapped at the outermost bi-layer, but...
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    Defect management for EUV without pellicles: extra exposures for wafer inspection

    At this year's International Conference on Extreme Ultraviolet Lithography, in Monterey, California, a Plenary paper was featured by Harry Levinson and Timothy Brunner, titled "Current challenges and opportunities for EUV lithography." It is available as an open access paper: Current challenges...
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    Samsung Exynos 9820: 8nm, dedicated NPU

    Samsung announced its Exynos 9820, which for the first time has a dedicated NPU: Samsung's next-gen Exynos 9820 chip adds dedicated AI for its 2019 phones. Manufactured on 8nm, it will go head-to-head against Apple's A12 and Huawei's Kirin 980, which are on TSMC 7nm. The Apple A12 also includes...
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    Brief summary/comparison of TSMC and Samsung EUV 7nm processes

    TSMC (N7+): - 1.2X density compared to N7 - up to 12% power reduction compared to N7 - up to 4 EUV layers - tracks assumed the same => N7 MMP=40 nm, assuming 10% reduction each direction gives 36 nm for N7+. Samsung (7LPP): Samsung...
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    Intel 14nm capacity issue

    There have been reports, such as DigiTimes: Intel To Outsource 14nm Chips To TSMC (Updated), of Intel 14nm capacity being insufficient, linked to 10nm delays, and even driving a second source in TSMC (using their 10nm?) It seems to suggest some of Intel's original 14nm capacity got converted to...
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    Samsung 7LPP a "2nd Gen" 7nm

    VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM – WikiChip Fuse This WikiChip fuse article which appeared several days ago is a pretty nice short review of Samsung's 7nm presentations from both VLSI 2018 and ISSCC 2018. It also seems to provide a pretty balanced look at Samsung's 7nm situation...
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    Intel's 10nm metal patterning contradiction - differences of hyper-NA tools?

    In this 22 nm presentation (p. 37), Intel reported 80 nm metal pitch with single patterning: However, in the 10nm IEDM 2017 paper, 40 nm metal pitch (20 nm half-pitch) was...
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    Samsung Electronics' Investors Forum - June 4 2018

    Samsung Electronics held an Investors Forum June 4 2018 in Singapore. The transcript is available here: Regarding semiconductor process updates, it is quite brief, here is what was mentioned in that script: 1. Risk produce 11LPP...
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    TSMC started shipping 7nm in Q2, process environmentally approved

    EIA for TSMC fab at Central Science Park approved - Taipei Times Apparently, last week, the Central Taiwan Science Park Administration received approval from the Environmenal Protection Administration for the Environmental Impact Analysis (EIA) report, updated for TSMC's 7nm process. TSMC...
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    The Impact of 3D Mask Effects on EUV Lithography

    In photolithography, it is common to imagine the photomask as a 2D screen with parts that block light and parts that transmit light. While this picture has its origins from long ago, it is no longer an accurate depiction in advanced lithography nodes, in particular for extreme ultraviolet...
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    TSMC 10nm CPP and MMP (from WikiChip)

    MMP for TSMC 10nm looks pretty close to 7nm (40 nm): 10 nm lithography process - WikiChip
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    Stochastic effects in EUV lithography: CD variability, printing failures (IMEC paper)

    I came across an excellent review of stochastic effects involved in EUV lithography, in a paper by Peter De Bisschop of IMEC, published in the Oct-Dec 2017 issue of Journal of Micro/Nanolithography, MEMS, and MOEMS. In this post, (with his permission of course) I only briefly summarize the...