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My guess is he is just an old man stuck in his ways, and when he was making his bones in the industry he worked at TI in the time of rot in the US semi industry (and I suppose US manufacturing in general) when the Japanese were doing just about everything better (except for I guess maybe logic...
Where was that announced? It also seems really weird for the Israel fabs to stay only on 7 given the new shell they've been building there. It seems weird for the 18A and 4 to be Ireland (rather than 4/3). Same deal with AZ too. One things for sure even without foundry disag is indeed causing...
Yeah I don't think you can find anyone who would say the process tech was in a great place for BDW or ICL, nevermind CNL (even if I think it would be funny to see it plotted here). Either way skylake and tigerlake were very clearly fine on the yield front given how intel made a boatload of those...
I think to really be secure they as Dan said need to follow intel to the canned Ft. Worth Texas Fab. Building a fab in Sherman next to good ol' TI would also be an essential step.
https://www.tomshardware.com/news/intel-details-core-ultra-meteor-lake-architecture-launches-december-14
In the process section intel prettied up their VLSI graphs. Besides the eye candy the more interesting thing is that MTL yields are better than at the Skylake or Tigerlake launches on the...
The 20A wafer shown was claimed to be an Arrow wafer. No mention was made of what the Lunar lake chip was made from.
I don’t recall them talking about which SKUs were launching. Did I miss this?
They already mentioned that they were designing a custom chip for them last quarter. So I don’t see...
I think there is an argument that innovation is faster today then the times of yore. TSMC 65nm was 30-50% PPW. 40nm was 40% PPW and 50% Power @iso Perf. 28nm was 20% and 40% respectively. On a 2-3 year cadence from 65>40nm>28 this gives ~17% PPW uplift per year. N3E>N2 is ~7% annual improvement...
They aren’t explicitly called out as VTFETs. The papers he is referring to all came from universities and are titled something to the tune of monolithic 3D cmos, cmos 2.0, and the most well developed concept paper was called skybridge. I am pretty sure all of the work has been very basic proof...
And those examples show the exact avenue that other firms use to pry open the clam. Wintel was based on an open hardware ecosystems vs the proprietary IBM PC/mainframe world. ARM's story was also all about offering an ease of use/openness that no prior ISA had. Linux won the unix wars as well as...
And that would be why. Obviously N3 is a more mature process than N3E at the moment. But I would have to assume that either at an equivalent maturity level N3E will yield better or at the very least will have a lower DD floor than N3. Costs per wafer and cycle times would also be lower, as will...
We’ve had this very discussion before. Every single BSP paper out there uses tungsten not copper. Scotten has talked about resistance from chipmakers on BPR due to the fact that the tungsten gets laid out first. But you must keep in mind if it was copper then this technology would go from...
I think the thing that had folk's panties in a bunch was the modest transistor count increase relative to the advertised density. Although I think most of these folks miss that due to the extended stay at N4 die sizes bloated up. Makes sense that on the new node Apple would want to go back to...
Samsung and SK also have large fabs in the PRC. 1 nand for Samsung and 1 of each for SK. From a US geopolitical angle the Micron fab in TW isn’t great, but the HVM sites in Singapore, Malyasia, and Japan are much “safer” (as well as being dispersed incase by some fluke something bad happens to...
To me, what this shows is increasing process capability and better integration to make up for higher process complexity. Obviously there is no way to know what parts of a given node that TSMC had to work the hardest to get working; but it is possible that this plot is just showing TSMC becoming...
I point you all to the intel 4 paper which has similar pitches to a hypothetical SMIC 5nm. They said without EUV mask layers or mask counts (I don’t remember) would increase 30% over intel 7. As a result I would have to assume that defect density and wafer cost on SMIC 5 would be crazy high.
You are then mixing BEOL processing and FEOL processing, which is a big fat no no. 3D NAND gets away with it b/c the array is built inside the beol, and the process of making the transistors is different than periphery/logic/dram feols.
As far as I understand intel’s public packaging roadmap forveros direct doesn’t exist yet, so no. My guess is that TSMC doesn’t have the hybrid bonding capacity to support intel and is too busy with fixing cows supply to fix this issue.
Yup we’re on the same wavelength here.
I hadn’t considered LELE. Based on my limited understanding, that might work; but we are so far beyond my expertise to tell you if there are any issues with that.
I don’t think so Fred. Fin pitches at that node were in the low/mid 30s. DUV direct print is at best 80nm. I don’t think 80nm ribbons would easily fit within a 272nm ish HD cell without having very tight gate to gate spacing. Although admittedly I don’t really have any data to back that up given...
I wish the SE used a cutdown SOC rather than a old chassis for this very reason. But I get why, designing a second weaker SOC is expensive/hard/increases the software burden alot when you support the chips for as long as Apple does.
