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Search results

  1. D

    Will we ever see STMicro or GF offer 7nm-class chips?

    Unless we find a technology to significantly reduce EUV costs + applications which requires tons of sub-7nm chips(+with little IP ecosystem), It's unlikely.
  2. D

    ASML reportedly sees first big EUV equipment order cut from TSMC

    Apart from the actual impact of the technology(either it's really powerful or not), Foundries can't change processes that fast. Massive changes in design rules will break businesses.
  3. D

    Samsung 3nm 1st generation reaches 'stable' yield, in mass production

    I think they always compared their 3GAE with their 5nm process and it showed somewhat lacking density improvements, but had more than a generation upgrade power efficiency. So this is expected a long ago. I'm actually quite curious about how 3GAP will work. Can it achieve density improvements...
  4. D

    Gordon Moore, Intel Co-Founder, Dies at 94

    People who made a giant company which make things smaller and smaller. What a journey.
  5. D

    Does the Micron layering technology have value in other semis?

    3D NAND-like stacking works only because it's designed to fight near the storage market. It has a large access granularity(like 4~16kB), so you have little routing difficulties. Basically same thing everywhere. You can etch deep, deposit....etc creating ~100 layers of NAND cell at once and fill...
  6. D

    What Happens When Shrink Ends?

    In some ways, shrinking ended a long ago. There were the good old days when one could simply rely on a Dennard scaling. Then diffraction kicks in, used OPC to mitigate...etc etc. Then clock speed limits kick in, strained silicon is introduced in Fab and wide superscalar is introduced from the...
  7. D

    How real is for GF, UMC, and other 2nd tier foundries to field a common sub-40nm platform?

    By theory, everything's possible. But there will be someone winning and someone losing. Since every 2nd tier foundry has different transistors, their customers are all accustomed to their foundries. If somehow foundries form some sort of alliance, then some fabless will be crying out loud, if a...
  8. D

    Samsung Electronics losing billions of dollars on chips

    Unlike foundry businesses, DRAM's a commodity. They have some variations like power...etc, but you can simply replace them if the price per performance is OK. In other words, you can steal customers via price war. Meanwhile, Samsung is enjoying a bit of cost superiority and TONS of cash($100B)...
  9. D

    Transistor performance for "3nm" class nodes in 2023 and early 2024.

    Oh sorry for the confusion. I meant Intel 7 on the second graph. I somehow thought that Intel's going to run IFS starting with i3(thus no information of curve with i7 node), but thinking back why not. Old architectures will work OK with Intel's last non-EUV nodes. Thank you for the great comparison!
  10. D

    Transistor performance for "3nm" class nodes in 2023 and early 2024.

    So Intel(or whatever IFS customer) has an ARM designed on Intel 7 as well? Never thought this kind of comparison is possible. Anyway, I kinda think that Intel is the one who can benefit from TSMC's FinFlex-like approach since they pack up high-density cores and high-performance cores in the same...
  11. D

    How Important is RISK V to the Semi Ecosystem?

    It may become important, if it finds workloads which 'only RISC-V' can achieve. It will not be replacing ARM from the mobile market, or x86 from the server market. Designing new compilers to frameworks just to work with new ISA is pretty much overkill(and it will not work) for most customers...
  12. D

    Single fin device DTCO

    That'll require more R&D expenditure. If TSMC tries to provide 'super' single fin device in 3nm node, then it'll not be 3nm anymore. You need to implement new contacts suited for that 'new' fins, dummy fin distance changes...etc it'll come at a price.
  13. D

    High-NA might be last-gen litho

    GAA helps by opening up new scaling paths. N-P distance reduction(no more dummies), gate length reduction(thanks to better leakage control), and CFET(N-P stacking). We can also consider GAA as a 'vertically stacked multi-fin device', making multi-fin device use 1-fin space by stacking up. It's...
  14. D

    High-NA might be last-gen litho

    Hard times indeed. It took more than 10 years to adopt EUV from ArF-i. Tons of new technologies, from materials to methodologies were required to introduce EUVs to Fabs. Even with these efforts, EUVs still suffer from throughput and power consumption. I'm not even sure if High NA EUVs really...
  15. D

    Will Memory Chiplets Dominate

    Chiplet approach these days mostly means emulating monolithic power-perf while keeping separate manufacturing facilities. Most memory applications don't really need that because memory doesn't need to be integrated 'together'. CPU or GPU(any controllers) can access memory wherever they are and...
  16. D

    NAND tech comparison

    YMTC's approach is quite different compared to others'. They use additional CMOS wafer to implement pheripheral logics. This give them additional density boost to cell wafers and better speed to interface but extra CMOS wafer and metal layers can be burdening(Other companies are using PUC). Not...
  17. D

    Is it true that Intel has the best packaging technology?

    They were the ones who emphasized the importance of advanced packaging first, but somehow their execution was kind of meh. EMIB was supposed to win against traditional MCM packaging which AMD Ryzen did(with extreme optimization though), we still don't see mainstream products with EMIB yet. On...
  18. D

    TechInsights standard cell height benchmark: Intel, Samsung, TSMC

    Hmm...quite surprised to see Samsung cell height here. The graph doesn't show us how capable each fin is, but at least they 'can' make small fins(apart from various schemes like SDB, COAG...etc). Maybe that's one of the reasons why parametric yields were horrible.
  19. D

    Are Samsung’s 3nm GAA Volume Production Yields Closer to 25% or 70%

    So it's more like Intel Loihi 2 production. Intel used their early 4nm fab to produce small neuromorphic chips. Maybe same purpose(learning curve).
  20. D

    What news sources do Semi professionals use to keep themselves current?

    There are good articles in LinkedIn and YouTube is flooding with Webinar. Much better than newspapers without professional proofreading.