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Many good comments here. Fabs exist in a tension between wafer outs (the manufacturing side) and tool uptime (engineering or maintenance), with process and yield acting as kind of referees. Some unscheduled downs are accepted since they can lead to profitable outcomes (more wafers produced)...
For the rest of the story. Skywater has an existing relationship with IMEC. See Skywater Florida facility. Senator Young played a key role in shepherding CHIPS, in collaboration with Senator Schummer. You can be certain that public monies will flow to IN, even though extant programs are nowhere...
IBM was my largest customer for many years. Novellus/LAM plating, CMP, X-ray photomasks, and many other things came out of IBM. I add that they were a benevolent force, compared to their brethren whoc can,t be bothered to attend conferences, let alone organize them. Of course, that "culture" was...
I had not considered that detail. I am not sure how or if ICs would have been broken out for firms making AND using their own chips. Can't see why they would. It's a good comment but too late to incorporate into my panel. I know for a fact that IBM's pursuit of semi technology (in the present)...
You are correct - I overstated the case. OEMs are the unsung heroes in this thing. As to your larger point, the US is an innovator but it's weak in implementation in terms of actual chip making. Blame high costs, blame Wall Street, blame business models, blame all three!
If you think about...
@jms_embedded The article by Williams and Khan is very good. You can see the consensus building. The critical comments about the science policy approach of the 90s (the so-called road map that we all followed) was most interesting. The establishment of NSTC could lead to the same outcome and not...
Because CHIPS is driven by National Security considerations, issues of the past (when defense purchases were larger as a %) get conflated with issues of today (AI for military purposes could become a strategic weapons systems according to some analysts). In other words:
1- Defense was a big...
@jms_embedded Thanks a lot. Very enlightening. This is what I had written but without data to back it up:
The military was an early adopter of solid-state technology, first in guidance systems and radio, and gradually into everything else. In early years, chips sold for military applications...
Thanks - I will make sure I read it. I think that going forward, the US military is concerned about maintaining its dominance indefinitely, particularly in the area of AI (for pilotless fighters for example - there are many others). AI is done with chips so you need to restrict chip sales (the...
@Tanj I had the wrong official title! This is the real title: Unintended Consequences of Government Subsidies on Moore’s Law and the Future of Semiconductors... Sorry for the error. See you in Saratoga I hope.
CHIPS refers to the US subsidy program. Nothing to do with ICs! You will need to attend ASMC to find out but I suspect the panelists will say that it may not be a good idea to build factories in high cost areas (e.g. the US) as it could end up weakening the underlying companies and limiting...
@Tanj My full sentence should have read "plenty of customers so that the factory(ies) is full all the time". In my mind, with the new mega factories, this implies being a foundry unless Apple is your customer and they buy 100% of your output. Intel's model relies on building large factories but...
@Tanj Thanks for that. Good insights. Much of the rhetoric in the USA is that invented the transistor, we invented the IC, DRAM, etc. That is true but is tangential to the requirements of successful manufacturing in today's world: large factories, plenty of customers to full all the time (so...
I am in charge of upcoming ASMC panel discussion. We are bringing together experts to talk about "unintended consequences of CHIPS on Moore's Law". I need to put together a few strong graphics but I am having difficulty locating long-series data. Here is specifically what I am looking for:
1-...
That's where P1, P2 etc. come in. You have effectively separate factories sharing staff and utilities. I think that logic and memory have different optimum sizes BTW.
Because you have other tools in between the tools and because fo dispatching with re-entrant flows. Example of tool between tools: CD-SEM or cleaning tools. You are trying to minimize the overall travel time on average. Say you go from Litho to PVD to Plating to CMP to Clean, the position...
Excellent feedback. You placed me on another related track. The transit time to go between tool A and tool B is another important metric. Adding steps increases that time and making the fab infinitely large would also increase that transit time.
Like everything in our business, it's delicate...
Good point, thanks.
To summarize, we have # of wafers, yield, # of steps and linewidth. Competitive foundry would need to optimize the first 3 (leaving litho aside for now). So I want the yield to be as high as possible with the least # of steps (not too many cleans for example), making sure...
