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Sorry - have I had too many experiences with Synopsys and other IP companies?
Each time I discuss the detailed particulars of a semiconductor company's implementation, I agree not to share that information. The information is limited to my review and use and not for public dissemination?
The Papers were presented at the Conference yes. We demonstrated the switching on site although it was only a bridge at the time.
I agree that the nature of the implementation is confusing. Particularly if you view it from traditional networking. (there is no network - only the "effect" of one)...
I can share Architecture Specifications under NDA - It's a hard thing to dump into the world without a modicum of security.
The ASIC designer who wrote it is a bit of an expert in Peripheral Switching so its been tested.
My challenge has been implementing it in order to get the "AHA" moment.
Totally Awesome Cliff
.... but it might be where I fear I lose everyone. ;-)
The switching fabric/arrangement itself does not require a CPU, nor SERDES, and we have no SRAM requirement.
The open digital CPO design from Ranovus is an ideal implementation as it would integrate direct from the OE...
Constructing secure peer data connectivity for mobile systems
Re-envisioning digital architectures connecting CE hardware for security, reliability and low energy
I am calculating to a 4GHz speed. The design is not constrained to a specific clock - connections will dictate. I use 4 GHz to...
Saw your post - yes a simulation power estimate is best.
I continue to struggle to keep up with things - I have a working method that requires the use of semiconductor designs - and yet zero experience in semiconductor / engineering.
I am very lucky the design is super simple.
If you can send me an email at firstname.lastname@example.org - I can send you a standard one.
I am working on raising some money later in the year - it is all bootstrapped - so disregard the mess in websites lol.
Just a general NDA so that there are no issues in the patent filing process. The paper doesnt get too much in depth and once the details are filed into USPTO then the it will establish prior art. Looking to register non-public status for the next month or so.
There are four - and focused on consumer implementations - and each is relatively similar. Applications move to Data Center and Semiconductor.
Sure - as soon as I lock in a customer / investor.
Immediately we are implementing a 4-port USB consumer data exchange switch using the FPGA - 40ns cross-switch latency at 100MHz. It is developed using the eFinnix platform which has lots of edge IOs for IoT. Considering the USB controller...
The FPGA power estimation for the switch logic is provided by the FPGA Manufacturer - this would be a third-party estimate and a more reliable / independent assessment. I will have my engineer take a simulation reading as well.
I feel waaaay out of place with my ~20 block PowerPoint design. Granted such specifications rely heavily on those analog automated routing solutions. ;-) I could look at printing it on much thicker paper so as to qualify for the billions of funding.
I have some work to show @Tanj and others, but I am all in on my view to cutting transistor counts by 10s to 100s of millions to deliver more data with less power and latency.
My view is that the industry will grasp the potential cut through much of the complexity with 'intelligent'...
@Tanj - sure - we do have a granted patent on the method. It is obscured in the fact we implemented first with USB - hardly a conspicuous Data Center implementation. I will have an updated kitchen sink filing within the month that has a more direct applications for data centers and semiconductor...
Describing my understanding of networking science as lean is fair - and I would add "rushed' and "haphazard". Without the 20-40 years of network engineering experience, I am trying to explain how this platform works by relying on a 1990's data communications course from my MBA - a peripheral...
The design is to eliminate queuing so no overprovisioning required. Also - the goal is to keep everything to a single hop. For now, we constrained the design to 100% capacity so there is no tailing latency as there is a perfect balance between throughput and demand.
10 million cores is a real...
Ok - too much too fast. Got it.
A dragonfly cabling arrangement is a direct data topology ... I was trying to say that this is what we create - a direct point-to-point data path - implemented dynamically and temporarily. A cross-over cable is a cable that has had the internal wires crossed...
@Tanj - Good points - and completely within the realm of current engineering approaches.
In addition to my earlier explanation: Our design does not over provision - only 100% of potential data exchange is implemented. Like the Google example - this is like Ai routing or circuit creation, but...