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Search results

  1. S

    Does the Micron layering technology have value in other semis?

    Stress management is a huge problem and also the yield is better. Not having the memory stack over logic makes stress management easier. Samsung showed it on their roadmap at IEDM a couple year ago. My belief is as we get above 500 layers everyone will go that way.
  2. S

    Does the Micron layering technology have value in other semis?

    YMTC uses 2 wafers and likely everyone will migrate to that approach eventually with logic on one wafer and the memory array on the other substrate.
  3. S

    Does the Micron layering technology have value in other semis?

    There are multiple approaches to 3D DRAM but the one getting the most attention at the device manufacturers has a stack of layers that are all patterned together. There is an approach where each layer is patterned and then they are bonded together but it is unlikely to be cost effective.
  4. S

    Samsung and SK Hynix Memory Production in China Issue

    I am sure they will but it will take time, my point is that the current export controls are creating an immediate issue particularly for SK Hynix.
  5. S

    Samsung and SK Hynix Memory Production in China Issue

    I think it will help Micron and Samsung on the DRAM side because it will constrain what SK Hynix can do in China and SK Hynix is also encountering long delays in their Yongin fab complex. Micron is planning new Fabs in the US but currently the majority of their memory is made in Asia.
  6. S

    Samsung and SK Hynix Memory Production in China Issue

    Per Digitimes Asia "Samsung, SK Hynix might not be able to produce next-gen memory in China in 3-5 years, warns expert". I find this pretty funny, SK Hynix has a big DRAM plant in China. SK Hynix has already ramped up their 1a DRAM outside of China using EUV, their inability to utilize EUV in...
  7. S

    Fab manufacturing questions

    Optimizing Factory Performance by Ignizio is a pretty good book but not semiconductor specific and I have seen comments from him that show he doesn't understand the unique aspect of semiconductor manufacturing.
  8. S

    Fab manufacturing questions

    "for example: if litho machines are $120M each and etch machines are $10M each and you get approximately the same cycle-time/throughput behavior from 4 litho tools + 20 etch tools = $680M, or 5 litho tools + 12 etch tools = $720M, then you're going to pick the $680M case." I don't think that...
  9. S

    Fab manufacturing questions

    There are essentially no operators in a 300mm fab, too few to matter. Wafers are all moved in FOUPs by overhead transport systems so idle no operator is a thing of the past, Decisions on what to process are all handled by automation too. I believe unscheduled down time is the biggest issue. It...
  10. S

    Fab manufacturing questions

    I would also say the state of the art fabs get to mature manufacturing performance in the first year or so and after that improvements are incremental, not "huge".
  11. S

    Fab manufacturing questions

    I disagree, a well designed fab will balance the tools across the fab to the greatest extent possible because the "constraint" will move, designing a deliberate constraint under utilizes everything else. How well that can be done is highly dependent on the fab size, the bigger the fab the better...
  12. S

    Fab manufacturing questions

    This is a surprisingly complex subject. I remember back in the late nineties at the Advanced Semiconductor Manufacturing Conference there was a lot of talk about the Theory of Constraints and everyone was reading "The Goal" by Eliyahu M. Goldratt. There was at least one company who designed a...
  13. S

    HKMG on DRAM nodes

    HKMG is used in the periphery for high performance DRAM. Samsung started making DRAM with and without HKMG beginning at 1x, Micron at 1z and SK Hynix at 1a. Samsung 1x is 7 years old, HKMG isn't that recent an addition. It is only used when needed for performance due to the cost sensitivity of DRAM.
  14. S

    The viability of CFET alternatives?

    I took that same course at IEDM, I also know Paul pretty well. With all due respect to Paul, a few comments. "As I'm sure you have heard, simple dimensional scaling (aka Moore's Law) is running out of steam, and DTCO approaches are required to keep scaling on track." What Gordon Moore...
  15. S

    The viability of CFET alternatives?

    Imec developed an incredibly dense vertical FET (VFET) SRAM with a relatively simple process flow years ago and my understanding is no one is interested in it. As far as I can tell none of the leading edge logic companies are working on vertical FETs. When I first saw it I thought it would be a...
  16. S

    Minimum number of M2 tracks over a standard cell

    Yes i4 is 3 fins and 5 tracks, they really squeezed the cell boundaries and n-p spacing
  17. S

    Minimum number of M2 tracks over a standard cell

    GLOBALFOUNDRIES 7nm paper at IEDM 2017 was 6 tracks as I wrote about here: https://semiwiki.com/semiconductor-manufacturers/intel/7191-iedm-2017-intel-versus-globalfoundries-at-the-leading-edge/
  18. S

    Minimum number of M2 tracks over a standard cell

    I don't completely understand it myself, I will touch base with someone I know at Imec. I thought I had a general idea but I am not so sure now. By the way, what is GF7?
  19. S

    The viability of CFET alternatives?

    I don't have specific numbers for 8nm, I just picked that because it is the last generation before EUV at the foundries. The key point to me is resistance was always an issue but a manageable one and it wasn't until recently that it became such a problem that people started looking at solutions...
  20. S

    The viability of CFET alternatives?

    Forksheet is basically making a HNS into a FinFET turned on it's side and you lose some electrostatic control
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