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Search results

  1. C

    TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

    Can somebody provide the met5, met6 pitch for the 5nm and 3nm process?
  2. C

    The cost penalty: Why auto chips are still in shortage

    We can migrate from ts16 to gf14 in a few days, ts40 to ts16 in a few weeks. RTL doesn't need to migrate. Analog topologies migrate somewhat, but you need to tune. Layout locations stay the same'ish, but needs to recompact, and the routes need to be totally redone. Now if you really want to...
  3. C

    The cost penalty: Why auto chips are still in shortage

    TSMC "removes the risk of you going to another foundry without physical redesign if you leave 40nm." How? "I bet they will stay 40, or even do a process refresh, but only for a few chosen big clients they know they can lose." You are probably correct. The little guys getting access to the TSMC...
  4. C

    The cost penalty: Why auto chips are still in shortage

    Great points Paul. That's what I thought when we automated 65nm and 40nm, but then the foundry gods exclaimed "Act like engineers, Suck it up, and move on!" I love 40g, but not if TSMC isn't going to let us MPW it. Circuit designers should embrace the ability expand their horizons with new...
  5. C

    TW local elections

    My worry is about the pro unification party winning.
  6. C

    TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

    Daniel, that was a great explanation of how the we have gotten to this point and answered a lot of questions. I hope to one day work in the land of giants, but for now I can only help the poor souls who can afford sub $3M NRE ASICs, so I will ask the same question again that I asked in the...
  7. C

    The cost penalty: Why auto chips are still in shortage

    JMS (can I call you Mr. Tandy?), I didn't want to call your company a dinosaur... well, actually I used to, but you guys have made some good purchases and have hired some good IC designers that I know, so you guys may have advanced to the late 1990s. I knew your employer well in 2010. We did a...
  8. C

    The cost penalty: Why auto chips are still in shortage

    We are just providing the EDA tools (front to back), tunable analog IP (serdes, PLLs, etc) that can be torn apart and pieced together differently, and the ASIC layout services. Our digital P&R is not novel. It is the same as what was done 30 years ago. We call it the "It's so easy, an analog...
  9. C

    The cost penalty: Why auto chips are still in shortage

    "1) Planning to enter the analog market" I would say we intend to help the 1-5 man electronic companies develop a high performance chip. These chips have analog and digital (mixed signal). We have both analog and digital (place and route) automation. They need both. "2) With 300mm wafers...
  10. C

    TW local elections

    Uh-oh. Paul, are you Taiwanese? Should we be worried about this?
  11. C

    The cost penalty: Why auto chips are still in shortage

    Nghayahem.... YES, and even to 16-12nm. I expect pushback my former neanderthal colleges, but I am going to say it. I have transitioned to being a cannibal intent on pushing analog stick-in-the-muds into retirement. Analog/Mixed-signal automation has arrived on double patterned finfet...
  12. C

    TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

    Great article. Thanks for pointing it out. I have a working knowledge of GF and TSMC 12 and above, but know nothing on Intel and processes below 16-12nm. This gives me an idea of what to expect, but the poly pitch minimum isn't the most critical dimension within a geometry node IMO. Routability...
  13. C

    How are gate counts measured?

    Assume about 5 or 6 poly-gates per cell, N and P. So if he polygate pitch is 100nm, and the stdcell height is 500nm, then the average logic cell area = 0.5um * 0.6um
  14. C

    How are gate counts measured?

    I think they mean logic cells, like nand gate, nor gate, etc.
  15. C

    TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

    Nghayanem might have gotten the numbers from here ... https://semiwiki.com/semiconductor-manufacturers/intel/6713-14nm-16nm-10nm-and-7nm-what-we-know-now" (Scotten Jones) The Intel rules are tighter, but probably painful to pass the DRCs, correct? Is it worth it? Does TSMC make it easier for...
  16. C

    TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

    They moved to double patterning, finfets, and routable contact layers. Huge benefits. These foundries have made mind-boggling progress. Please expand on Intel's density on 16nm vs TSMC. Is one process geared for yield, the other for performance (oxide thickness, for example)? Gate pitch? Via...
  17. C

    TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

    Thank you for clarifying. I was concerned that we spent too many man years automating train-wrecked processes.
  18. C

    Ken Griffin warns U.S. faces ‘immediate Great Depression’ if China seizes Taiwan’s semiconductor industry

    Good discussion. I haven't figured out if I agree with all of you or none of you, but dictators seem to be men of action. Why risk takeovers, earthquakes, sabotage, etc? Companies should second source.
  19. C

    TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

    Paul, can you expand on "TSMCs 16nm-28nm train wreck"?
  20. C

    Chip-Making Juggernaut TSMC Eyes Multibillion-Dollar Arizona Factory Expansion

    Thanks Ben. Do you (or anybody) have a prediction on TSMC's interposer capability in AZ? For example, flipchipping onto an interposer with HBM2/3 probably needs to be done at a foundry (I called Amkor. They referred me to the foundries below 90nm). We can't design for just the SOC anymore. I...
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